Patents by Inventor Krishna Bhuwalka
Krishna Bhuwalka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11705521Abstract: Semiconductor devices are provided. A semiconductor device includes a fin structure having a plurality of first semiconductor patterns and a plurality of second semiconductor patterns alternately stacked on a substrate, and extending in a first direction. The semiconductor device includes a semiconductor cap layer on an upper surface of the fin structure, and extending along opposite side surfaces of the fin structure in a second direction crossing the first direction. The semiconductor device includes a gate electrode on the semiconductor cap layer, and extending in the second direction. The semiconductor device includes a gate insulating film between the semiconductor cap layer and the gate electrode. Moreover, the semiconductor device includes a source/drain region connected to the fin structure. The plurality of first semiconductor patterns include silicon germanium (SiGe) having a germanium (Ge) content in a range of 25% to 35%, and the plurality of second semiconductor patterns include silicon (Si).Type: GrantFiled: December 23, 2021Date of Patent: July 18, 2023Inventors: Sanghoon Lee, Krishna Bhuwalka, Myunggil Kang, Kyoungmin Choi
-
Publication number: 20220115539Abstract: Semiconductor devices are provided. A semiconductor device includes a fin structure having a plurality of first semiconductor patterns and a plurality of second semiconductor patterns alternately stacked on a substrate, and extending in a first direction. The semiconductor device includes a semiconductor cap layer on an upper surface of the fin structure, and extending along opposite side surfaces of the fin structure in a second direction crossing the first direction. The semiconductor device includes a gate electrode on the semiconductor cap layer, and extending in the second direction. The semiconductor device includes a gate insulating film between the semiconductor cap layer and the gate electrode. Moreover, the semiconductor device includes a source/drain region connected to the fin structure. The plurality of first semiconductor patterns include silicon germanium (SiGe) having a germanium (Ge) content in a range of 25% to 35%, and the plurality of second semiconductor patterns include silicon (Si).Type: ApplicationFiled: December 23, 2021Publication date: April 14, 2022Inventors: Sanghoon Lee, Krishna Bhuwalka, Myunggil Kang, Kyoungmin Choi
-
Patent number: 11217695Abstract: Semiconductor devices are provided. A semiconductor device includes a fin structure having a plurality of first semiconductor patterns and a plurality of second semiconductor patterns alternately stacked on a substrate, and extending in a first direction. The semiconductor device includes a semiconductor cap layer on an upper surface of the fin structure, and extending along opposite side surfaces of the fin structure in a second direction crossing the first direction. The semiconductor device includes a gate electrode on the semiconductor cap layer, and extending in the second direction. The semiconductor device includes a gate insulating film between the semiconductor cap layer and the gate electrode. Moreover, the semiconductor device includes a source/drain region connected to the fin structure. The plurality of first semiconductor patterns include silicon germanium (SiGe) having a germanium (Ge) content in a range of 25% to 35%, and the plurality of second semiconductor patterns include silicon (Si).Type: GrantFiled: March 11, 2020Date of Patent: January 4, 2022Inventors: Sanghoon Lee, Krishna Bhuwalka, Myunggil Kang, Kyoungmin Choi
-
Patent number: 10868125Abstract: A semiconductor device includes an active pattern provided on a substrate and a gate electrode crossing over the active pattern. The active pattern includes a first buffer pattern on the substrate, a channel pattern on the first buffer pattern, a doped pattern between the first buffer pattern and the channel pattern, and a second buffer pattern between the doped pattern and the channel pattern. The doped pattern includes graphene injected with an impurity.Type: GrantFiled: August 6, 2019Date of Patent: December 15, 2020Inventors: Mirco Cantoro, Zhenhua Wu, Krishna Bhuwalka, Sangsu Kim, Shigenobu Maeda
-
Publication number: 20200381555Abstract: Semiconductor devices are provided. A semiconductor device includes a fin structure having a plurality of first semiconductor patterns and a plurality of second semiconductor patterns alternately stacked on a substrate, and extending in a first direction. The semiconductor device includes a semiconductor cap layer on an upper surface of the fin structure, and extending along opposite side surfaces of the fin structure in a second direction crossing the first direction. The semiconductor device includes a gate electrode on the semiconductor cap layer, and extending in the second direction. The semiconductor device includes a gate insulating film between the semiconductor cap layer and the gate electrode. Moreover, the semiconductor device includes a source/drain region connected to the fin structure. The plurality of first semiconductor patterns include silicon germanium (SiGe) having a germanium (Ge) content in a range of 25% to 35%, and the plurality of second semiconductor patterns include silicon (Si).Type: ApplicationFiled: March 11, 2020Publication date: December 3, 2020Inventors: Sanghoon Lee, Krishna Bhuwalka, Myunggil Kang, Kyoungmin Choi
-
Publication number: 20190363163Abstract: A semiconductor device includes an active pattern provided on a substrate and a gate electrode crossing over the active pattern. The active pattern includes a first buffer pattern on the substrate, a channel pattern on the first buffer pattern, a doped pattern between the first buffer pattern and the channel pattern, and a second buffer pattern between the doped pattern and the channel pattern. The doped pattern includes graphene injected with an impurity.Type: ApplicationFiled: August 6, 2019Publication date: November 28, 2019Inventors: Mirco Cantoro, Zhenhua Wu, Krishna Bhuwalka, Sangsu Kim, Shigenobu Maeda
-
Patent number: 10418448Abstract: A semiconductor device includes an active pattern provided on a substrate and a gate electrode crossing over the active pattern. The active pattern includes a first buffer pattern on the substrate, a channel pattern on the first buffer pattern, a doped pattern between the first buffer pattern and the channel pattern, and a second buffer pattern between the doped pattern and the channel pattern. The doped pattern includes graphene injected with an impurity.Type: GrantFiled: May 10, 2017Date of Patent: September 17, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Mirco Cantoro, Zhenhua Wu, Krishna Bhuwalka, Sangsu Kim, Shigenobu Maeda
-
Patent number: 10014395Abstract: A fin tunnel field effect transistor includes a seed region and a first type region disposed above the seed region. The first type region includes a first doping. The fin tunnel field effect transistor includes a second type region disposed above the first type region. The second type region includes a second doping that is opposite the first doping. The fin tunnel field effect transistor includes a gate insulator disposed above the second type region and a gate electrode disposed above the gate insulator. A method for forming an example fin tunnel field effect transistor is provided.Type: GrantFiled: April 3, 2017Date of Patent: July 3, 2018Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventor: Krishna Bhuwalka
-
Publication number: 20170243942Abstract: A semiconductor device includes an active pattern provided on a substrate and a gate electrode crossing over the active pattern. The active pattern includes a first buffer pattern on the substrate, a channel pattern on the first buffer pattern, a doped pattern between the first buffer pattern and the channel pattern, and a second buffer pattern between the doped pattern and the channel pattern. The doped pattern includes graphene injected with an impurity.Type: ApplicationFiled: May 10, 2017Publication date: August 24, 2017Inventors: Mirco Cantoro, Zhenhua Wu, Krishna Bhuwalka, Sangsu Kim, Shigenobu Maeda
-
Publication number: 20170207328Abstract: A fin tunnel field effect transistor includes a seed region and a first type region disposed above the seed region. The first type region includes a first doping. The fin tunnel field effect transistor includes a second type region disposed above the first type region. The second type region includes a second doping that is opposite the first doping. The fin tunnel field effect transistor includes a gate insulator disposed above the second type region and a gate electrode disposed above the gate insulator. A method for forming an example fin tunnel field effect transistor is provided.Type: ApplicationFiled: April 3, 2017Publication date: July 20, 2017Inventor: Krishna Bhuwalka
-
Patent number: 9679975Abstract: A semiconductor device includes an active pattern provided on a substrate and a gate electrode crossing over the active pattern. The active pattern includes a first buffer pattern on the substrate, a channel pattern on the first buffer pattern, a doped pattern between the first buffer pattern and the channel pattern, and a second buffer pattern between the doped pattern and the channel pattern. The doped pattern includes graphene injected with an impurity.Type: GrantFiled: August 11, 2015Date of Patent: June 13, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Mirco Cantoro, Zhenhua Wu, Krishna Bhuwalka, Sangsu Kim, Shigenobu Maeda
-
Patent number: 9614049Abstract: A fin tunnel field effect transistor includes a seed region and a first type region disposed above the seed region. The first type region includes a first doping. The fin tunnel field effect transistor includes a second type region disposed above the first type region. The second type region includes a second doping that is opposite the first doping. The fin tunnel field effect transistor includes a gate insulator disposed above the second type region and a gate electrode disposed above the gate insulator. A method for forming an example fin tunnel field effect transistor is provided.Type: GrantFiled: June 20, 2013Date of Patent: April 4, 2017Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventor: Krishna Bhuwalka
-
Publication number: 20160141373Abstract: A semiconductor device includes an active pattern provided on a substrate and a gate electrode crossing over the active pattern. The active pattern includes a first buffer pattern on the substrate, a channel pattern on the first buffer pattern, a doped pattern between the first buffer pattern and the channel pattern, and a second buffer pattern between the doped pattern and the channel pattern. The doped pattern includes graphene injected with an impurity.Type: ApplicationFiled: August 11, 2015Publication date: May 19, 2016Inventors: Mirco Cantoro, Zhenhua Wu, Krishna Bhuwalka, Sangsu Kim, Shigenobu Maeda
-
Publication number: 20160086841Abstract: A method for forming a pattern of a semiconductor device and a semiconductor device formed using the same are provided. The method includes forming a buffer layer on a substrate, forming a channel layer on the buffer layer, forming support patterns penetrating the channel layer, and forming channel fin patterns and a buffer pattern by patterning the channel layer and the buffer layer. The channel layer includes a material of which a lattice constant is different from that of the buffer layer, and each of the channel fin patterns has both sidewalls that are in contact with the support patterns and are opposite to each other.Type: ApplicationFiled: May 13, 2015Publication date: March 24, 2016Inventors: SEUNGHYUN SONG, Hyeon Kyun Noh, Taeyong Kwon, Sangsu Kim, Shigenobu Maeda, Krishna Bhuwalka, Uihui Kwon, Keunho Lee, Wonsok Lee
-
Publication number: 20140374799Abstract: A fin tunnel field effect transistor includes a seed region and a first type region disposed above the seed region. The first type region includes a first doping. The fin tunnel field effect transistor includes a second type region disposed above the first type region. The second type region includes a second doping that is opposite the first doping. The fin tunnel field effect transistor includes a gate insulator disposed above the second type region and a gate electrode disposed above the gate insulator. A method for forming an example fin tunnel field effect transistor is provided.Type: ApplicationFiled: June 20, 2013Publication date: December 25, 2014Inventor: Krishna Bhuwalka
-
Patent number: 8916927Abstract: Among other things, one or more techniques for forming a vertical tunnel field effect transistor (FET), and a resulting vertical tunnel FET are provided herein. In an embodiment, the vertical tunnel FET is formed by forming a core over a first type substrate region, forming a second type channel shell around a circumference greater than a core circumference, forming a gate dielectric around a circumference greater than the core circumference, forming a gate electrode around a circumference greater than the core circumference, and forming a second type region over a portion of the second type channel shell, where the second type has a doping opposite a doping of the first type. In this manner, line tunneling is enabled, thus providing enhanced tunneling efficiency for a vertical tunnel FET.Type: GrantFiled: July 19, 2012Date of Patent: December 23, 2014Assignee: Taiwan Semiconductor ManufacturingInventors: Krishna Bhuwalka, Gerben Doornbos, Matthias Passlack
-
Publication number: 20140021532Abstract: Among other things, one or more techniques for forming a vertical tunnel field effect transistor (FET), and a resulting vertical tunnel FET are provided herein. In an embodiment, the vertical tunnel FET is formed by forming a core over a first type substrate region, forming a second type channel shell around a circumference greater than a core circumference, forming a gate dielectric around a circumference greater than the core circumference, forming a gate electrode around a circumference greater than the core circumference, and forming a second type region over a portion of the second type channel shell, where the second type has a doping opposite a doping of the first type. In this manner, line tunneling is enabled, thus providing enhanced tunneling efficiency for a vertical tunnel FET.Type: ApplicationFiled: July 19, 2012Publication date: January 23, 2014Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: Krishna Bhuwalka, Gerben Doornbos, Matthias Passlack