Abstract: In a pipelined processor, a method and apparatus for performing restoration of the previous values of young bits in the annex after a mispredicted branch has been detected. In a first embodiment, beginning with the oldest annex entry, the destination register address of that entry is broadcast to all other entries. All annex entries with matching addresses have their young bits reset, while the young bits of the broadcast entry is set. The above broadcast, compare, reset, and set operations are performed on all the remaining valid entries sequentially and in order of decreasing age. When all valid entries have been broadcast, the young bit states are correctly reconstructed. In a second embodiment, each annex entry has a current young bit Y0 and one or more past young bits (Y1 through YN). For branch condition resolutions which take up to N clock cycles, N past young bits are maintained in each annex entry.