Patents by Inventor Krishna Chaithanya Gurram

Krishna Chaithanya Gurram has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Robust hamming code implementation for soft error detection, correction, and reporting in a multi-level cache system using dual banking memory scheme
    Patent number: 8904260
    Abstract: The invention is a memory system having two memory banks which can store and recall with memory error detection and correction on data of two different sizes. For writing separate parity generators form parity bits for respective memory banks. For reading separate parity detector/generators operate on data of separate memory banks.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: December 2, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Jonathan (Son) Hung Tran, Abhijeet Ashok Chachad, Joseph Raymond Michael Zbiciak, Krishna Chaithanya Gurram
  • Hazard prevention for data conflicts between level one data cache line allocates and snoop writes
    Patent number: 8856446
    Abstract: A comparator compares the address of DMA writes in the final entry of the FIFO stack to all pending read addresses in a monitor memory. If there is no match, then the DMA access is permitted to proceed. If the DMA write is to a cache line with a pending read, the DMA write access is stalled together with any DMA accesses behind the DMA write in the FIFO stack. DMA read accesses are not compared but may stall behind a stalled DMA write access. These stalls occur if the cache read was potentially cacheable. This is possible for some monitored accesses but not all. If a DMA write is stalled, the comparator releases it to complete once there are no pending reads to the same cache line.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: October 7, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Abhijeet Ashok Chachad, Jonathan (Son) Hung Tran, Raguram Damodaran, Krishna Chaithanya Gurram
  • Configurable source based/requestor based error detection and correction for soft errors in multi-level cache memory to minimize CPU interrupt service routines
    Patent number: 8707127
    Abstract: This invention is a memory system with parity generation which selectively forms and stores parity bits of corresponding plural data sources. The parity generation and storage depends upon the state of a global suspend bit and a global enable bit, and parity detection/correction corresponding to each data source.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: April 22, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Jonathan (Son) Hung Tran, Abhijeet Ashok Chachad, Raguram Damodaran, Krishna Chaithanya Gurram
  • Hazard Prevention for Data Conflicts Between Level One Data Cache Line Allocates and Snoop Writes
    Publication number: 20120198162
    Abstract: A comparator compares the address of DMA writes in the final entry of the FIFO stack to all pending read addresses in a monitor memory. If there is no match, then the DMA access is permitted to proceed. If the DMA write is to a cache line with a pending read, the DMA write access is stalled together with any DMA accesses behind the DMA write in the FIFO stack. DMA read accesses are not compared but may stall behind a stalled DMA write access. These stalls occur if the cache read was potentially cacheable. This is possible for some monitored accesses but not all. If a DMA write is stalled, the comparator releases it to complete once there are no pending reads to the same cache line.
    Type: Application
    Filed: September 28, 2011
    Publication date: August 2, 2012
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Abhijeet Ashok Chachad, Jonathan (Son) Hung Tran, Raguram Damodaran, Krishna Chaithanya Gurram
  • CONFIGURABLE SOURCE BASED/REQUESTOR BASED ERROR DETECTION AND CORRECTION FOR SOFT ERRORS IN MULTI-LEVEL CACHE MEMORY TO MINIMIZE CPU INTERRUPT SERVICE ROUTINES
    Publication number: 20120198310
    Abstract: This invention is a memory system with parity generation which selectively forms and stores parity bits of corresponding plural data sources. The parity generation and storage depends upon the state of a global suspend bit and a global enable bit, and parity detection/correction corresponding to each data source.
    Type: Application
    Filed: September 23, 2011
    Publication date: August 2, 2012
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jonathan (Son) Hung Tran, Abhijeet Ashok Chachad, Raguram Damodaran, Krishna Chaithanya Gurram
  • Robust Hamming Code Implementation for Soft Error Detection, Correction, and Reporting in a Multi-Level Cache System Using Dual Banking Memory Scheme
    Publication number: 20120192027
    Abstract: The invention is a memory system having two memory banks which can store and recall with memory error detection and correction on data of two different sizes. For writing separate parity generators form parity bits for respective memory banks. For reading separate parity detector/generators operate on data of separate memory banks.
    Type: Application
    Filed: September 23, 2011
    Publication date: July 26, 2012
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jonathan (Son) Hung Tran, Abhijeet Ashok Chachad, Joseph Raymond Michael Zbiciak, Krishna Chaithanya Gurram