Patents by Inventor Krishna Chandra

Krishna Chandra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240121555
    Abstract: An audio system is for a motor vehicle having a passenger compartment. The system includes a plurality of microphones disposed in the passenger compartment and each producing a respective microphone signal indicative of audible voices in the passenger compartment. A plurality of loudspeakers are disposed in the passenger compartment and emit sounds based on infotainment audio signals. An audio processor receives the microphone signals, and determines from the microphone signals respective locations of people in the passenger compartment who are participating in a voice conversation. The audio processor modifies the infotainment audio signals sent to individual ones of the loudspeakers based on the determined locations such that the sounds emitted by the loudspeakers are quieter as heard by the people participating in the voice conversation than as heard by at least one other person in the passenger compartment.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 11, 2024
    Inventor: ANANTHA KRISHNA CHANDRA SHEKAR RAO
  • Patent number: 11392519
    Abstract: A method of determining a configuration state of an I/O module connected to a fieldbus controller is disclosed, the method comprising the steps of receiving from the I/O module a key ID, comparing the key ID with at least one key ID stored on the fieldbus controller, and configuring the I/O module when the received key ID does not correspond to the at least one stored key ID stored. Further, a circuit for configuring a digital input of a fieldbus controller as either a PNP input or an NPN input is provided comprising a control circuit including a reference input, a first selection input, and a control output. The circuit also comprises a data circuit including a second selection input electrically connected to the control output, a data input electrically coupled to the digital input, and a data output.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: July 19, 2022
    Assignee: Parker-Hannifin Corporation
    Inventors: Erick Rudaitis, Krishna Chandra Moulik, Shameer Padinhare Kandi Meethal, Sachin Vithoba Naik
  • Patent number: 11120036
    Abstract: Described herein are systems and methods for providing access to a database in a multi-tenant environment, including the use of a connection pool, with support for efficient repurposing of connections. In accordance with an embodiment, a software application can request that a connection be provided, to enable access to the database. In response to receiving the request, the connection pool can first determine if a particular connection with the exact desired attributes already exists within the pool, but is borrowed at the time of the request. If such a connection exists, then the connection pool can wait a period of time for that particular connection to become available, referred to herein as a double-wait. Subsequently, if the particular connection is not made available within the double-wait time period, the connection pool resumes its usual operation, for example by repurposing other connections.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: September 14, 2021
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Jean de Lavarene, Yuri Dolgov, Vidya Hegde, Saurabh Verma, Krishna Chandra, Aramvalarthanathan Namachivayam
  • Publication number: 20200364166
    Abstract: A method of determining a configuration state of an I/O module connected to a fieldbus controller is disclosed, the method comprising the steps of receiving from the I/O module a key ID, comparing the key ID with at least one key ID stored on the fieldbus controller, and configuring the I/O module when the received key ID does not correspond to the at least one stored key ID stored. Further, a circuit for configuring a digital input of a fieldbus controller as either a PNP input or an NPN input is provided comprising a control circuit including a reference input, a first selection input, and a control output. The circuit also comprises a data circuit including a second selection input electrically connected to the control output, a data input electrically coupled to the digital input, and a data output.
    Type: Application
    Filed: January 29, 2019
    Publication date: November 19, 2020
    Inventors: Erick RUDAITIS, Krishna CHANDRA MOULIK, Shameer PADINHARE KANDI MEETHAL, Sachin VITHOBA NAIK
  • Publication number: 20180245943
    Abstract: A method of providing navigation information in a motor vehicle includes the following computer-implemented steps. Received from a user is an identity of a destination that the user would like to go to. It is determined that the destination is not a parking area. Ascertained is a location of a parking area within a threshold distance of the destination. The user is asked if he would like to go to the parking area instead of the destination. Received from the user is an indication that he would like to go to the parking area instead of the destination. In response to receiving the indication from the user, navigation guidance information is provided to arrive at the parking area.
    Type: Application
    Filed: February 13, 2018
    Publication date: August 30, 2018
    Inventors: ANANTHA KRISHNA CHANDRA, ANNAMALAI PARAMASIVAM
  • Publication number: 20180135998
    Abstract: A method of enabling a driver to provide inputs to a vehicle while driving includes installing a tactile input device within the vehicle. A first portion of a set of inputs is received from the driver via the tactile input device. An increase in difficulty of a driving task of the driver is sensed. In response to the sensing step, the driver is automatically audibly prompted to enter a second portion of the set of inputs via an auditory input device. The second portion of the set of inputs is received from the driver via the auditory input device.
    Type: Application
    Filed: November 14, 2017
    Publication date: May 17, 2018
    Inventors: ANNAMALAI PARAMASIVAM, ANANTHA KRISHNA CHANDRA, JOHN HOLDREN
  • Publication number: 20180039628
    Abstract: Described herein are systems and methods for providing access to a database in a multi-tenant environment, including the use of a connection pool, and support for dynamic relocation of tenants. In accordance with an embodiment, a software application can obtain a connection from the connection pool, on behalf of a tenant, which enables the software application or tenant to access the database. A relocation process enables a tenant which is associated with a multi-tenant or other client application, to be relocated within the database environment, for example across a plurality of container databases, with near-zero downtime to the client application, including managing the draining of existing connections, and the migrating of new connections, without requiring changes to the underlying application.
    Type: Application
    Filed: August 3, 2016
    Publication date: February 8, 2018
    Inventors: Jean de Lavarene, Saurabh Verma, Vidya Hegde, Krishna Chandra, Aramvalarthanathan Namachivayam
  • Publication number: 20180039678
    Abstract: Described herein are systems and methods for providing access to a database in a multi-tenant environment, including the use of a connection pool, with support for efficient repurposing of connections. In accordance with an embodiment, a software application can request that a connection be provided, to enable access to the database. In response to receiving the request, the connection pool can first determine if a particular connection with the exact desired attributes already exists within the pool, but is borrowed at the time of the request. If such a connection exists, then the connection pool can wait a period of time for that particular connection to become available, referred to herein as a double-wait. Subsequently, if the particular connection is not made available within the double-wait time period, the connection pool resumes its usual operation, for example by repurposing other connections.
    Type: Application
    Filed: August 3, 2016
    Publication date: February 8, 2018
    Inventors: Jean de Lavarene, Yuri Dolgov, Vidya Hegde, Saurabh Verma, Krishna Chandra, Aramvalarthanathan Namachivayam
  • Patent number: 9348995
    Abstract: A memory device package encloses two separate die, one being a standard nonvolatile memory integrated circuit (“IC”) die, and the other being any suitable authentication IC die. Either die may be stacked upon the other, or the die may be placed side-by-side. The external contacts may correspond to the power and signal requirements of the standard nonvolatile memory IC die so that the pin-out of the memory device package may present a standard pinout. The power and signal requirements of the authentication IC die may be satisfied with some or all of the pins for the nonvolatile memory integrated circuit die, or with other unused pins of the device package. One or more additional external contacts may be added exclusively for the authentication integrated circuit die. One or more signals may be dedicated as between the standard nonvolatile memory IC die and the authentication IC die.
    Type: Grant
    Filed: May 7, 2015
    Date of Patent: May 24, 2016
    Assignee: WINBOND ELECTRONICS CORPORATION
    Inventors: Ming-Huei Shieh, Krishna Chandra Shekar, Hui Chen
  • Publication number: 20150310203
    Abstract: A memory device package encloses two separate die, one being a standard nonvolatile memory integrated circuit (“IC”) die, and the other being any suitable authentication IC die. Either die may be stacked upon the other, or the die may be placed side-by-side. The external contacts may correspond to the power and signal requirements of the standard nonvolatile memory IC die so that the pin-out of the memory device package may present a standard pinout. The power and signal requirements of the authentication IC die may be satisfied with some or all of the pins for the nonvolatile memory integrated circuit die, or with other unused pins of the device package. One or more additional external contacts may be added exclusively for the authentication integrated circuit die. One or more signals may be dedicated as between the standard nonvolatile memory IC die and the authentication IC die.
    Type: Application
    Filed: May 7, 2015
    Publication date: October 29, 2015
    Inventors: Ming-Huei Shieh, Krishna Chandra Shekar, Hui Chen
  • Patent number: 9053317
    Abstract: A memory device package encloses two separate die, one being a standard nonvolatile memory integrated circuit (“IC”) die, and the other being any suitable authentication IC die. Either die may be stacked upon the other, or the die may be placed side-by-side. The external contacts may correspond to the power and signal requirements of the standard nonvolatile memory IC die so that the pin-out of the memory device package may present a standard pinout. The power and signal requirements of the authentication IC die may be satisfied with some or all of the pins for the nonvolatile memory integrated circuit die, or with other unused pins of the device package. One or more additional external contacts may be added exclusively for the authentication integrated circuit die. One or more signals may be dedicated as between the standard nonvolatile memory IC die and the authentication IC die.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: June 9, 2015
    Assignee: WINBOND ELECTRONICS CORPORATION
    Inventors: Ming-Huei Shieh, Krishna Chandra Shekar, Hui Chen
  • Patent number: 8969924
    Abstract: Various aspects of the invention are directed to memory circuits and their implementation. According to an example embodiment, an apparatus includes a channel region between raised source and drain regions which are configured and arranged with respective bandgap offsets relative to the channel region to confine carriers in the channel region. The apparatus also includes front and back gates respectively separated from the channel region by gate dielectrics. The raised source and drain regions have respective portions laterally adjacent the front gate and adjacent the channel region. Carriers are stored in the channel region via application of voltage(s) to the front and back gates, and relative to bias(es) at the source and drain regions.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: March 3, 2015
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Ashish Pal, Aneesh Nainani, Krishna Chandra Saraswat
  • Patent number: 8933488
    Abstract: In accordance with one or more embodiments, an apparatus and method involves a channel region, barrier layers separated by the channel region and a dielectric on one of the barrier layers. The barrier layers have band gaps that are different than a band gap of the channel region, and confine both electrons and holes in the channel region. A gate electrode applies electric field to the channel region via the dielectric. In various contexts, the apparatus and method are amenable to implementation for both electron-based and hole-based implementations, such as for nmos, pmos, and cmos applications.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: January 13, 2015
    Assignee: The Board of Trustees of the Leland Stanford Junior Univerity
    Inventors: Aneesh Nainani, Krishna Chandra Saraswat
  • Publication number: 20140245384
    Abstract: A memory device package encloses two separate die, one being a standard nonvolatile memory integrated circuit (“IC”) die, and the other being any suitable authentication IC die. Either die may be stacked upon the other, or the die may be placed side-by-side. The external contacts may correspond to the power and signal requirements of the standard nonvolatile memory IC die so that the pin-out of the memory device package may present a standard pinout. The power and signal requirements of the authentication IC die may be satisfied with some or all of the pins for the nonvolatile memory integrated circuit die, or with other unused pins of the device package. One or more additional external contacts may be added exclusively for the authentication integrated circuit die. One or more signals may be dedicated as between the standard nonvolatile memory IC die and the authentication IC die.
    Type: Application
    Filed: February 28, 2013
    Publication date: August 28, 2014
    Applicant: WINBOND ELECTRONICS CORPORATION
    Inventors: Ming-Huei Shieh, Krishna Chandra Shekar, Hui Chen
  • Publication number: 20130307025
    Abstract: Various aspects of the invention are directed to memory circuits and their implementation. According to an example embodiment, an apparatus includes a channel region between raised source and drain regions which are configured and arranged with respective bandgap offsets relative to the channel region to confine carriers in the channel region. The apparatus also includes front and back gates respectively separated from the channel region by gate dielectrics. The raised source and drain regions have respective portions laterally adjacent the front gate and adjacent the channel region. Carriers are stored in the channel region via application of voltage(s) to the front and back gates, and relative to bias(es) at the source and drain regions.
    Type: Application
    Filed: February 22, 2013
    Publication date: November 21, 2013
    Applicant: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Ashish Pal, Aneesh Nainani, Krishna Chandra Saraswat
  • Publication number: 20120138899
    Abstract: In accordance with one or more embodiments, an apparatus and method involves a channel region, barrier layers separated by the channel region and a dielectric on one of the barrier layers. The barrier layers have band gaps that are different than a band gap of the channel region, and confine both electrons and holes in the channel region. A gate electrode applies electric field to the channel region via the dielectric. In various contexts, the apparatus and method are amenable to implementation for both electron-based and hole-based implementations, such as for nmos, pmos, and cmos applications.
    Type: Application
    Filed: December 1, 2011
    Publication date: June 7, 2012
    Inventors: Aneesh Nainani, Krishna Chandra Saraswat
  • Patent number: 8064239
    Abstract: Data is stored in a quantum-well type structure with double gate control. According to an example embodiment, a transistor-based data storage circuit includes a gate, a back gate and a semiconductor channel between the gate and the back gate. Carriers are stored in a storage pocket structure in the channel, in response to biases applied to the gate and back gate. Current passing through the channel is sensed and used to detect the stored carriers and, correspondingly, a memory state of the storage circuit.
    Type: Grant
    Filed: November 12, 2009
    Date of Patent: November 22, 2011
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Mehmet Günhan Ertosun, Krishna Chandra Saraswat, Pawan Kapur
  • Publication number: 20100149864
    Abstract: Data is stored in a quantum-well type structure with double gate control. According to an example embodiment, a transistor-based data storage circuit includes a gate, a back gate and a semiconductor channel between the gate and the back gate. Carriers are stored in a storage pocket structure in the channel, in response to biases applied to the gate and back gate. Current passing through the channel is sensed and used to detect the stored carriers and, correspondingly, a memory state of the storage circuit.
    Type: Application
    Filed: November 12, 2009
    Publication date: June 17, 2010
    Inventors: Mehmet Günhan Ertosun, Krishna Chandra Saraswat, Pawan Kapur
  • Patent number: 7728387
    Abstract: Various semiconductor devices and methods of manufacture are employed. According to an example embodiment of the present invention, a MOS-compatible semiconductor device exhibits high channel mobility and low leakage. The device includes a channel region having a high-mobility strained material layer and a tunneling mitigation layer on the strained material layer to mitigate tunnel leakage. The strained material has a lattice structure that is strained to match the lattice structure of the tunneling mitigation layer. An insulator layer is on the tunneling mitigation layer, and an electrode is over the insulator and adapted to apply a voltage bias to the channel region to switch the device between conductive and nonconductive states. Current is transported in the conductive state as predominantly facilitated via the mobility of the strained material layer, and wherein tunneling current in the nonconductive state is mitigated by the tunneling mitigation layer.
    Type: Grant
    Filed: June 12, 2007
    Date of Patent: June 1, 2010
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Tejas Krishnamohan, Krishna Chandra Saraswat
  • Patent number: 7131341
    Abstract: A method and apparatus for the detection of trace volatiles such as those produced by fungal decay of timber, comprising a sampling probe (10), comprising a housing (11) and bored barrel (12) adapted removably to receive an SPME device (14) in which a coated tipped fiber (15) is guided within a needle sheath (16) into the barrel (12), and a pump (19) is energized to draw a fluid sample over the fiber tip within the bore of the barrel. A motor (23) advances and retracts the SPME device (14) and its fiber (15) for a sample to be captured thereby and the captured sample is then released within an instrument having an array of gas sensors whereby any trace volatiles captured by and released from the coated fiber (15) may then be analyzed by computer software to produce a fingerprint for the location and identification of the presence of trace volatiles at a site into which the sampling probe is introduced.
    Type: Grant
    Filed: October 20, 2005
    Date of Patent: November 7, 2006
    Assignee: Peter Cox Limited
    Inventors: Peter Darren Wareham, Krishna Chandra Persaud