Abstract: A memory module includes one or more memory devices, a memory interface to a host computer, and a memory overprovisioning logic. The memory overprovisioning logic is configured to monitor memory usage of the one or more memory devices and provide a compression and/or deduplication ratio of the memory module to a kernel driver module of the host computer. The kernel driver module of the host computer is configured to update a virtual memory capacity of the memory module based on the compression and/or deduplication ratio.

Abstract: A memory module includes a host interface configured to provide an interface to a host computer; one or more memory devices; a deduplication engine configured to provide a virtual memory capacity of the memory module that is larger than a physical size of the one or more memory devices; a memory controller for controlling access to the one or more memory devices; a volatile memory comprising a hash table, an overflow memory region, and a credit unit, wherein the overflow memory region stores user data when a hash collision occurs or the hash table is full, and wherein the credit unit stores an address of an invalidated entry in the overflow memory region; and a control logic is configured to control the overflow memory region and the credit unit and generate a warning indicating a status of the overflow memory region and the credit unit.

Abstract: A method for migrating a workload includes: receiving workloads generated from a plurality of applications running in a plurality of server nodes of a rack system; monitoring latency requirements for the workloads and detecting a violation of the latency requirement for a workload; collecting system utilization information of the rack system; calculating rewards for migrating the workload to other server nodes in the rack system; determining a target server node among the plurality of server nodes that maximizes the reward; and performing migration of the workload to the target server node.

Abstract: A deduplication memory module, which is configured to internally perform memory deduplication, includes a hash table memory for storing multiple blocks of data in a hash table array including hash tables, each of the hash tables including physical buckets and a plurality of virtual buckets each including some of the physical buckets, each of the physical buckets including ways, an address lookup table memory (ALUTM) including a plurality of pointers indicating a location of each of the stored blocks of data in a corresponding one of the physical buckets, and a buffer memory for storing unique blocks of data not stored in the hash table memory when the hash table array is full, a processor, and memory, wherein the memory has stored thereon instructions that, when executed by the processor, cause the memory module to exchange data with an external system.

Abstract: A dynamic random access memory (DRAM) processing unit (DPU) may include at least one computing cell array having a plurality of DRAM-based computing cells arranged in an array having at least one column in which the at least one column may include at least three rows of DRAM-based computing cells configured to provide a logic function that operates on a first and a second row of the at least three rows and configured to store a result of the logic function in a third row of the at least three rows; and a controller that may be coupled to the at least one computing cell array to configure the at least one computing cell array to perform a DPU operation.

Abstract: A system includes a library, a compiler, a driver and at least one dynamic random access memory (DRAM) processing unit (DPU). The library may determine at least one DPU operation corresponding to a received command. The compiler may form at least one DPU instruction for the DPU operation. The driver may send the at least one DPU instruction to at least one DPU. The DPU may include at least one computing cell array that includes a plurality of DRAM-based computing cells arranged in an array having at least one column in which the at least one column may include at least three rows of DRAM-based computing cells configured to provide a logic function that operates on a first row and a second row of the at least three rows and configured to store a result of the logic function in a third row of the at least three rows.

Abstract: An electronic system includes: a processor configured to access operation data; a local cache memory, coupled to the processor, configured to store a limited amount of the operation data; a memory controller, coupled to the local cache memory, configured to maintain a flow of the operation data; and a memory subsystem, coupled to the memory controller, including: a first tier memory configured to store the operation data, with critical timing, by a fast control bus, and a second tier memory configured to store the operation data with non-critical timing, by a reduced performance control bus.

Abstract: A dynamic random access memory (DRAM) processing unit (DPU) may include at least one computing cell array that may include a plurality of DRAM-based computing cells arranged in an array having at least one column in which the at least one column may include at least three rows of DRAM-based computing cells configured to provide a logic function that operates on a first row and a second row of the at least three rows and configured to store a result of the logic function in a third row of the at least three rows.

Abstract: A memory module has a logic including a programming register, a deduplication ratio control logic, and a deduplication engine. The programming register stores a maximum deduplication ratio of the memory module. The control logic is configured to control a deduplication ratio of the memory module according to the maximum deduplication ratio. The deduplication ratio is programmable by the host computer.

Abstract: A memory device includes a memory interface to a host computer and a memory overprovisioning logic configured to provide a virtual memory capacity to a host operating system (OS). A kernel driver module of the host OS is configured to manage the virtual memory capacity of the memory device provided by the memory overprovisioning logic of the memory device and provide a fast swap of anonymous pages to a frontswap space and file pages to a cleancache space of the memory device based on the virtual memory capacity of the memory device.

Abstract: A memory module includes one or more memory devices, a memory interface to a host computer, and a memory overprovisioning logic. The memory overprovisioning logic is configured to monitor memory usage of the one or more memory devices and provide a compression and/or deduplication ratio of the memory module to a kernel driver module of the host computer. The kernel driver module of the host computer is configured to update a virtual memory capacity of the memory module based on the compression and/or deduplication ratio.

Abstract: A thermal, flow measuring device for ascertaining a mass flow or a flow velocity of a medium in a pipe. The thermal, flow measuring device has at least one measuring transducer with at least a first and a second sensor element. The first sensor element has a pin-shaped metal sleeve, which has a lowest point on a wall of the metal sleeve in the gravitational direction, wherein there is arranged in the metal sleeve at least one heating means, especially a heatable temperature sensor. The heating means is arranged in the metal sleeve and above the aforementioned point in the gravitational direction, in such a manner that the maximum heat input per unit area from the heating means into the medium occurs in the gravitational direction above the point.

Abstract: A deduplication memory module, which is configured to internally perform memory deduplication, includes a hash table memory for storing multiple blocks of data in a hash table array including hash tables, each of the hash tables including physical buckets and a plurality of virtual buckets each including some of the physical buckets, each of the physical buckets including ways, an address lookup table memory (ALUTM) including a plurality of pointers indicating a location of each of the stored blocks of data in a corresponding one of the physical buckets, and a buffer memory for storing unique blocks of data not stored in the hash table memory when the hash table array is full, a processor, and memory, wherein the memory has stored thereon instructions that, when executed by the processor, cause the memory module to exchange data with an external system.

Abstract: A method of retrieving data stored in a memory associated with a dedupe module is provided. The method includes: identifying a logical address of the data; identifying a physical line ID of the data in accordance with the logical address by looking up at least a portion of the logical address in a translation table; locating a respective physical line, the respective physical line corresponding to the PLID; and retrieving the data from the respective physical line, the retrieving including copying a respective hash cylinder to the read cache, the respective hash cylinder including: a respective hash bucket, the respective hash bucket including the respective physical line; and a respective reference counter bucket, the respective reference counter bucket including a respective reference counter associated with the respective physical line.

Abstract: A dedupe module is provided. The dedupe module includes: a host interface; a dedupe engine to receive a data request from a host system via the host interface; a memory controller; a plurality of memory modules, each memory module being coupled to the memory controller; and a read cache for caching data from the memory controller for use by the dedupe engine.

Abstract: A memory (1205) is disclosed. The memory (1205) can includes a stack of dynamic Random Access Memory (DRAM) cores (1210, 1215, 1220, 1225) in a three-dimensional stacked memory architecture (1230). Each of the DRAM cores (1210, 1215, 1220, 1225) can include a plurality of banks (205-1, 205-2, 205-3, 205-4) to store data. The memory (1205) can also include logic layer (1235) which can include an interface (1305) to connect the memory (1205) with a processor (120). The logic layer (1235) can also include a refresh engine (115) that can be used to refresh one of the plurality of banks (205-1, 205-2, 205-3, 205-4) and a Smart Refresh Component (305) that can advise the refresh engine (115) which bank to refresh using an out-of-order per-bank refresh. The Smart Refresh Component (305) can use a logic (415) to identify a farthest bank in the pending transactions in the transaction queue (430) at the time of refresh.

Abstract: An electronic system includes: an interface block of a storage device configured to process system information from a system device; a memory block of the storage device, coupled to the interface block, partitioned by the interface block configured to process the system information for partitioning the memory block; and a storage block of a storage device, coupled to the memory block, configured to access a data block of the storage block provided to the system device.

Abstract: An electronic system includes: a processor configured to access operation data; a local cache memory, coupled to the processor, configured to store a limited amount of the operation data; a memory controller, coupled to the local cache memory, configured to maintain a flow of the operation data; and a memory subsystem, coupled to the memory controller, including: a first tier memory configured to store the operation data, with critical timing, by a fast control bus, and a second tier memory configured to store the operation data with non-critical timing, by a reduced performance control bus.

Abstract: A memory (1205) is disclosed. The memory (1205) can includes a stack of dynamic Random Access Memory (DRAM) cores (1210, 1215, 1220, 1225) in a three-dimensional stacked memory architecture (1230). Each of the DRAM cores (1210, 1215, 1220, 1225) can include a plurality of banks (205-1, 205-2, 205-3, 205-4) to store data. The memory (1205) can also include logic layer (1235) which can include an interface (1305) to connect the memory (1205) with a processor (120). The logic layer (1235) can also include a refresh engine (115) that can be used to refresh one of the plurality of banks (205-1, 205-2, 205-3, 205-4) and a Smart Refresh Component (305) that can advise the refresh engine (115) which bank to refresh using an out-of-order per-bank refresh. The Smart Refresh Component (305) can use a logic (415) to identify a farthest bank in the pending transactions in the transaction queue (430) at the time of refresh.

Abstract: A dynamic Random Access Memory (DRAM) module (105) is disclosed. The DRAM module (105) can includes a plurality of banks (205-1, 205-2, 205-3, 205-4) to store data and a refresh engine (115) that can be used to refresh one of the plurality of banks (205-1, 205-2, 205-3, 205-4). The DRAM module (105) can also include a Smart Refresh Component (305) that can advise the refresh engine (115) which bank to refresh using an out-of-order per-bank refresh. The Smart Refresh Component (305) can use a logic (415) to identify a farthest bank in the pending transactions in the transaction queue (430) at the time of refresh.