Abstract: An object relational map verification system is described. In some embodiments, the object relational map verification system can verify object relational maps and identify counterexamples when an object relational map cannot be verified. The object relational map verification system can verify an object relational map by (1) receiving objects, database schemas, query views, and update views; (2) generating first order logic formulae corresponding to the received objects, database schemas, query views, and update views; and (3) proving theorems indicated by the generated first order logic formulae. When the theorems are proved, the object relational map is verified. In some embodiments, the object relational map verification system can also generate models illustrating counterexamples when the theorem cannot be proved. The counterexamples provide data that the object relational map does not consistently store and then retrieve.

Abstract: An object relational map verification system is described. In some embodiments, the object relational map verification system can verify object relational maps and identify counterexamples when an object relational map cannot be verified. The object relational map verification system can verify an object relational map by (1) receiving objects, database schemas, query views, and update views; (2) generating first order logic formulae corresponding to the received objects, database schemas, query views, and update views; and (3) proving theorems indicated by the generated first order logic formulae. When the theorems are proved, the object relational map is verified. In some embodiments, the object relational map verification system can also generate models illustrating counterexamples when the theorem cannot be proved. The counterexamples provide data that the object relational map does not consistently store and then retrieve.

Abstract: A very long instruction word (VLIW) architecture describes a processor comprising multiple functional units operating in parallel. A very long instruction word contains a plurality of fields or issue slots for specifying which operations are to be performed by the functional units. Execution of an operation can be inhibited by a guard value specified in the issue slot. Instructions are dispatched in such a guarded VLIW architecture by routing one of a plurality of fields issued for a common functional unit based on the guard value. Thus, an instruction word may contain a greater number of issue slots than there are functional units.