Abstract: An electronic system includes a processor circuit, a memory circuit, and an error correction circuit. The error correction circuit receives information read from the memory circuit. The error correction circuit detects if the information contains an error. The error correction circuit corrects the error in the information to generate corrected information and provides the corrected information and an error signal to the processor circuit. The processor circuit provides the corrected information and a write command to the memory circuit based on the error signal indicating the error. The memory circuit overwrites the information stored in the memory circuit with the corrected information in response to the write command.

Abstract: An electronic system includes a processor circuit, a memory circuit, and an error correction circuit. The error correction circuit receives information read from the memory circuit. The error correction circuit detects if the information contains an error. The error correction circuit corrects the error in the information to generate corrected information and provides the corrected information and an error signal to the processor circuit. The processor circuit provides the corrected information and a write command to the memory circuit based on the error signal indicating the error. The memory circuit overwrites the information stored in the memory circuit with the corrected information in response to the write command.

Abstract: An integrated circuit includes a monitored circuit and a signal analyzer circuit. The signal analyzer circuit includes a logic circuit that determines if a condition signal satisfies a condition to generate an output signal. A first-in-first-out (FIFO) buffer circuit stores opportunistic data indicated by a monitored signal received from the monitored circuit in response to the output signal indicating if the condition signal satisfies the condition. A communication channel transmits the opportunistic data stored in the FIFO buffer circuit outside the integrated circuit.

Abstract: An apparatus and method for redundant data processing with graceful degrading functionality. For example, one embodiment of an apparatus comprises: three processing elements operable in a first redundancy mode, the three processing elements to execute a same sequence of instructions to produce three corresponding results; detection circuitry to detect when any one processing element of the three processing elements produces a different result from the other two processing elements of the three processing elements; tracking circuitry to associate an error with the one processing element when it produces the different result from the other two processing elements, wherein if an error threshold is reached for the one processing element, the other two processing elements are to operate in a second redundancy mode excluding the one processing element.

Abstract: An electronic system includes a processor circuit, a memory circuit, and an error correction circuit. The error correction circuit receives information read from the memory circuit. The error correction circuit detects if the information contains an error. The error correction circuit corrects the error in the information to generate corrected information and provides the corrected information and an error signal to the processor circuit. The processor circuit provides the corrected information and a write command to the memory circuit based on the error signal indicating the error. The memory circuit overwrites the information stored in the memory circuit with the corrected information in response to the write command.

Abstract: An integrated circuit includes a monitored circuit and a signal analyzer circuit. The signal analyzer circuit includes a logic circuit that determines if a condition signal satisfies a condition to generate an output signal. A first-in-first-out (FIFO) buffer circuit stores opportunistic data indicated by a monitored signal received from the monitored circuit in response to the output signal indicating if the condition signal satisfies the condition. A communication channel transmits the opportunistic data stored in the FIFO buffer circuit outside the integrated circuit.