Abstract: A device, system, and methods are described to perform machine-learning camera-based indoor mobile positioning. The indoor mobile positioning may utilize inexact computing, wherein a small decrease in accuracy is used to obtain significant computational efficiency. Hence, the positioning may be performed using a smaller memory overhead at a faster rate and with lower energy cost than previous implementations. The positioning may not involve any communication (or data transfer) with any other device or the cloud, providing privacy and security to the device. A hashing-based image matching algorithm may be used which is cheaper, both in energy and computation cost, over existing state-of-the-art matching techniques. This significant reduction allows end-to-end computation to be performed locally on the mobile device.

Abstract: A device, system, and methods are described to perform machine-learning camera-based indoor mobile positioning. The indoor mobile positioning may utilize inexact computing, wherein a small decrease in accuracy is used to obtain significant computational efficiency. Hence, the positioning may be performed using a smaller memory overhead at a faster rate and with lower energy cost than previous implementations. The positioning may not involve any communication (or data transfer) with any other device or the cloud, providing privacy and security to the device. A hashing-based image matching algorithm may be used which is cheaper, both in energy and computation cost, over existing state-of-the-art matching techniques. This significant reduction allows end-to-end computation to be performed locally on the mobile device.

Abstract: A device, system, and methods are described to perform machine-learning camera-based indoor mobile positioning. The indoor mobile positioning may utilize inexact computing, wherein a small decrease in accuracy is used to obtain significant computational efficiency. Hence, the positioning may be performed using a smaller memory overhead at a faster rate and with lower energy cost than previous implementations. The positioning may not involve any communication (or data transfer) with any other device or the cloud, providing privacy and security to the device. A hashing-based image matching algorithm may be used which is cheaper, both in energy and computation cost, over existing state-of-the-art matching techniques. This significant reduction allows end-to-end computation to be performed locally on the mobile device.

Abstract: Various embodiments of the resistive memory cells and arrays discussed herein comprise: (1) a first electrode; (2) a second electrode; (3) resistive memory material; and (4) a diode. The resistive memory material is selected from the group consisting of SiOx, SiOxNy, SiOxNyH, SiOxCz, SiOxCzH, and combinations thereof, wherein each of x, y and z are equal or greater than 1 or equal or less than 2. The diode may be any suitable diode, such as n-p diodes, p-n diodes, and Schottky diodes.

Abstract: Various embodiments of the resistive memory cells and arrays discussed herein comprise: (1) a first electrode; (2) a second electrode; (3) resistive memory material; and (4) a diode. The resistive memory material is selected from the group consisting of SiOx, SiOxH, SiOxNy, SiOxNyH, SiOxCz, SiOxCzH, and combinations thereof, wherein each of x, y and z are equal to or greater than 1 and equal to or less than 2. The diode may be any suitable diode, such as n-p diodes, p-n diodes, and Schottky diodes.

Abstract: Various embodiments of the resistive memory cells and arrays discussed herein comprise: (1) a first electrode; (2) a second electrode; (3) resistive memory material; and (4) a diode. The resistive memory material is selected from the group consisting of SiOx, SiOxH, SiOxNy, SiOxNyH, SiOxCz, SiOxCzH, and combinations thereof, wherein each of x, y and z are equal or greater than 1 or equal or less than 2. The diode may be any suitable diode, such as n-p diodes, p-n diodes, and Schottky diodes.

Abstract: A processor having binary switches is configured to operate at a predetermined probability value that the logical value of each switch is correct. A supply voltage is coupled to the binary switches. A randomized signal detector is configured to detect a randomized signal, which may be amplified to a predetermined level if the randomized signal is low. A computing element outputs a probabilistic binary bit having a 0 or 1 with a predetermined probability value of being correct in correspondence with the supply voltage and/or an amplification level of a noise signal. Subsequently, an application executed by the processor receives the probabilistic binary bit for one or more additional operations. By operating on the probabilistic binary bits instead of conventional deterministic bits, the processor consumes less energy and completes its execution faster. For battery-powered portable electronic devices, use of processor configured for probabilistic binary bits substantially lengthens battery life.

Abstract: The invention affords a system and method for programming a data processor having a microprocessor and reconfigurable logic, to attain high-speed performance while maintaining compatibility with current software programming practices by providing an API that makes the details of the interaction between the microprocessor and the reconfigurable logic units transparent to the compiler. The API virtualizes operations implemented within the reconfigurable logic unit as reconfigurable logic instructions (RL-instructions) which can be scheduled by the compiler in a manner similar to microprocessor instructions. The API provides methods for the microprocessor to configure the reconfigurable logic unit, transmit data to the reconfigurable logic unit, receive data from the reconfigurable logic unit, and otherwise interact with the reconfigurable logic unit.