Abstract: An improved ferroelectric, non-volatile memory comprises an array of ferroelectric capacitors with each capacitor connected to one row and one column select line through a network of diodes. The select lines are connected to a power supply or ground to access one of the cells. The diodes are configured to provide a conducting path between a power supply and ground including the accessed cell while isolating all other cells from the power supply and ground.

Abstract: A high speed picture element generator for use in a digital facsimile receiver for reforming picture elements from decoded facsimile transmission signals. The picture element generator receives the decoded facsimile signals in the form of run length data of sequential color units in a line of picture. An input register of the picture element generator receives the run length data of a color unit, and an output register holds the picture element data. A decoder, coupled to the input register, generates the picture element data for the output register from the run length data. The decoder is also coupled to the output register so that the generated picture data fills portions of the output register unoccupied by the picture element data of previous color units.

Abstract: A method and device for decoding two-dimensionally encoded digital facsimile signals. The method includes (a) accumulating the run lengths of color change picture elements in the reference line, (b) decoding a codeword to generate a displacement value, (c) combining the accumulated run length of a reference line color change picture element and a displacement value to obtain accumulated run lengths of coded line color change picture elements, and (d) determining the difference between accumulated run lengths of a coded line color change picture element. The difference is the decoded data.

Abstract: A method and device for two-dimensionally coding digital facsimile signals, especially for the CCITT T.4 recommended standard. A line of digitized picture elements is coded with respect to a reference line of digitized picture elements. The run lengths of color units previous to color change picture elements in the coding and reference lines are accumulated, and the positions of the color change picture elements in the coding line with respect to the positions of the color change picture elements in the reference line are determined by the differences between the accumulated run lengths of the coding and reference line color change picture element and the reference line color change picture elements. The steps are selectively repeated in predetermined sequences responsive to the value of the accumulated run length differences.

Abstract: A high speed facsimile device suitable for integration using present day VLSI technology, for encoding binarily digitized picture information into run length codes. The device receives consecutive blocks of digitized picture data. In the device a run length generator unit, which is responsive to these consecutive blocks of picture data, generates the run lengths of color units in a data block. A combining unit coupled to the run length generator unit combines the run lengths of color units in more than one data block and an encoding unit coupled to the run length generator block and the combining unit generates in a pre-determined code, such as the recommended CCITT T.4 standard, the coded run lengths of color units independent of the data blocks.

Abstract: An arithmetic logic register stack device is provided on a single semiconductor chip, which device comprises a building block for digital systems. The device of this invention is expandable, which enables performing operations with binary numbers greater than that with which a single device is capable of performing. Unique circuit design is provided for multiple use of connector pins to the semiconductor device, thereby allowing for an increase in the complexity of the circuits that can be integrated onto a single semiconductor chip or placed into a package with a given number of pins.

Abstract: A universal first-in first-out memory device is provided on a single semiconductor chip, which device may constitute a building block for digital systems. Provisions have been made in the device of this invention, as a result of unique circuit designs, to enable expansion of one memory device into an array of several memory devices to thereby expand the number of binary digits that can be stored, or the amount of data that can be stored in the array.