Abstract: Embodiments contained in the disclosure provide a method and apparatus for device specific thermal mitigation. The thermal and power behavior of the device, is characterized. A thermal threshold is then determined for the device. The thermal data and thermal ramp factor for each device are determined and stored in a cross-reference matrix. A correlation factor is determined for temperature and frequency. These correlation factors determine a device mitigation temperature. The device mitigation temperature may be stored in a fuse table on the device, with a fuse blown on the device to permanently store the device mitigation temperature. The apparatus includes: an electronic device, a memory within the electronic device, and a set of fuses within the electronic device. The device also includes means for determining if a static or dynamic frequency is high, and means for mitigating a voltage and frequency used by the device, based on that determination.

Abstract: Embodiments contained in the disclosure provide a method and apparatus for device specific thermal mitigation. The thermal and power behavior of the device, is characterized. A thermal threshold is then determined for the device. The thermal data and thermal ramp factor for each device are determined and stored in a cross-reference matrix. A correlation factor is determined for temperature and frequency. These correlation factors determine a device mitigation temperature. The device mitigation temperature may be stored in a fuse table on the device, with a fuse blown on the device to permanently store the device mitigation temperature. The apparatus includes: an electronic device, a memory within the electronic device, and a set of fuses within the electronic device. The device also includes means for determining if a static or dynamic frequency is high, and means for mitigating a voltage and frequency used by the device, based on that determination.

Abstract: Aspects of an integrated circuit (IC) using a scaling voltage are provided. The IC includes a chip section configured to operate using a scaled supply voltage. The IC also includes a sensor configured to measure a temperature of the chip section. The IC also includes an adjustment circuit configured to adjust a supply voltage to a scaled supply voltage, wherein the scaled voltage is based on the measured temperature. Aspects of a testing device for a chip are also provided. The testing device includes a sensor configured to measure an operating frequency of a section of the chip when operating at a defined temperature. The testing device also includes a memory device comprising a scaled voltage table, the scaled voltage table configured to store as an entry the measured operating frequency and the defined temperature.

Abstract: An apparatus includes a memory and at least one processor coupled to the memory is provided. The at least one processor is configured to read first information corresponding to an electrical characteristic of a first core on the at least one processor and second information corresponding to an electrical characteristic of a second core on the at least one processor and to select the first core or the second core for operation based on the first information and the second information. An integrated circuit on a substrate is provided. The integrated circuit includes a first core and a second core. A memory stores first information corresponding to an electrical characteristic of the first core and second information corresponding to an electrical characteristic of the second core. A default core includes the first core or the second core configured to read the first information and the second information.

Abstract: A multi-core processor comprising a plurality of cores, a plurality of core caches, each core cache associated with a single core, a plurality of low drop out (LDO) devices, each LDO device associated with a single core for scaling operating voltage to the core; and a memory for storing a lookup table that maps core operating frequency to core operating voltage, and a voltage scaling algorithm for determining a core specific voltage scaling factor for each cor. Each of the plurality of LDO devices applies the core specific voltage scaling factor determined by the algorithm. During operation, one core operates at a different operating voltage than a second core for the same operating frequency.