Abstract: A method and apparatus for automatically loading device status information into a network device. One embodiment comprises an apparatus in a network device, wherein the network device enters a sleep state under particular conditions. In one embodiment, the apparatus is for communicating with other devices on the network and comprises control circuitry that controls communication between the network device and the other devices on the network. The apparatus further comprises a memory device that stores configuration data for the control circuitry, wherein at least a portion of the configuration data is loaded into the control circuitry upon initialization of the network device. The apparatus further comprises a buffer that stores keep-alive data that is transmitted to a plurality of the other devices in the network to refresh the presence of the network device in the network, wherein the keep-alive data is loaded into the buffer from the memory device upon initialization of the network device.

Abstract: A scaleable priority arbiter for arbitrating between multiple FIFO entry points of a network interface card (NIC). The circuit provides a separate FIFO entry point circuit within the NIC for each data packet priority type. Exemplary priority types, from highest to lowest, include isochronous, priority 1, priority 2, . . . , priority n. A separate set of FIFO entry points are provided for NIC transmitting (Tx) and for NIC receiving (Rx). For each of the Tx FIFO entry points, a single Tx entry point register is seen by the processor and multiple downlist pointers are also maintained. The Tx entry point registers all feed a scaleable priority arbiter which selects the next message for transmission. The scaleable priority arbiter is made of scaleable circuit units that contain a sequential element controlling a multiplexer.

Abstract: A method and apparatus for automatically configuring a configurable integrated circuit. One embodiment comprises a method for automatically loading data including configuration data to a configurable integrated circuit upon initialization of a system in which the configurable integrated circuit is embedded. The method of one embodiment comprises storing a plurality of commands and a plurality of data elements in a non-volatile memory of the system. The method further comprises reading contents of an initial address in the non-volatile memory. If the initial address contains a command, depending upon a type of the command, the method comprises writing contents of a next address in the non-volatile memory to a register space of the configurable integrated circuit, to a configuration space of the configurable integrated circuit, or to a command space of the configurable integrated circuit.

Abstract: A transmit packet buffer (TPB) is used on a network interface card (NIC) to store downloaded packets and forward them through the media access controller (MAC) and the physical layer interface (PHY) onto the wire. A multi-function TPB is implemented to allow the multiple usage of this buffer. Packets may be downloaded to this buffer through multiple sources. Different types of the packets may each be stored at predefined locations. For example, while the second half of the TPB is used to transmit keep-alive or alert-on-LAN packets, the first half may be used to compare received packets with a wake-up pattern for system wake-up. With multi-function support, various PC management functions may be implemented more effectively and with reduced cost.

Abstract: A first-in-first-out (FIFO) entry point circuit for a network interface card. The novel circuit of the present invention provides a FIFO entry point circuit within a network interface card (NIC). The FIFO implementation allows multiple downlist pointers to be maintained within the transmit (Tx) FIFO entry point circuit and also allows multiple uplist pointers to be maintained for the receive (Rx) FIFO entry point circuit. For the Tx FIFO entry point circuit, only one register is visible to the processor which can load a memory pointer into the entry point thereby placing the memory pointer on the bottom on the FIFO. Only one register is seen for the Rx FIFO entry point circuit. With respect to the Tx FIFO entry point circuit, the NIC takes the oldest entry, obtains the packet from memory that is indicated by the corresponding pointer and transmits the packet onto a network.