Patents by Inventor Krishnakanth Sistia

Krishnakanth Sistia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8131940
    Abstract: Methods and apparatuses to support memory transactions using partial physical addresses are disclosed. Method embodiments generally comprise home agents monitoring multiple responses to multiple memory requests, wherein at least one of the responses has a partial address for a memory line, resolving conflicts for the memory requests, and suspending conflict resolution for the memory requests which match partial address responses until determining the full address. Apparatus embodiments generally comprise a home agent having a response monitor and a conflict resolver. The response monitor may observe a snoop response of a memory agent, wherein the snoop response only has a partial address and is for a memory line of a memory agent. The conflict resolver may suspend conflict resolution for memory transactions that match the partial address of the memory line until the conflict resolver receives a full address for the memory line.
    Type: Grant
    Filed: March 31, 2007
    Date of Patent: March 6, 2012
    Assignee: Intel Corporation
    Inventors: Krishnakanth Sistia, Yen-Cheng Liu
  • Patent number: 8117478
    Abstract: A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: February 14, 2012
    Assignee: Intel Corporation
    Inventors: Yen-Cheng Liu, P Keong Or, Krishnakanth Sistia, Ganapati Srinivasa
  • Publication number: 20080162972
    Abstract: A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.
    Type: Application
    Filed: December 29, 2006
    Publication date: July 3, 2008
    Inventors: Yen-Cheng Liu, P. Keong Or, Krishnakanth Sistia, Ganapati Srinivasa