Abstract: A magnetic memory cell in which a sensor is magnetically coupled to a magnetic media wherein the separation of the magnetic media from the sensor permits each to be magnetically optimized separate from the other, thus improving defect tolerance and minimizing the magnetic influence of neighboring cells in an array on one another. In an embodiment, the read circuitry is positioned so that no read current passes through the media during a read operation. In an alternative embodiment, processing is simplified but the read current is allowed to pass through the media.

Abstract: Embodiments of the present invention disclose an MRAM device having a plurality of magnetic memory cells grouped into words, and write conductors for carrying write currents to write to the memory cells, wherein at least some of the write conductors have a reduced cross-sectional area in the vicinity of a group of memory cells.

Abstract: Embodiments of the invention magnetic memory device, comprising: a magnetic tunnel junction (MTJ) which includes a Magnetic Tunnel Junction (MTJ) stack which has one of a crescent-shaped profile and an elbow-shaped profile in cross-section.

Abstract: Embodiments of the invention magnetic memory device, comprising: a magnetic tunnel junction (MTJ) which includes a first free layer optimized for reading; and a second free layer separate from the MTJ and optimized for writing.

Abstract: A novel magnetic memory cell utilizing nanotubes as conducting leads is disclosed. The magnetic memory cell may be built based on MTJ (Magnetic Tunnel Junction) or GMR (Giant Magneto Resistance) sensors or devices of similar nature. A SET (Single Electron Transistor) made of semiconducting nanotubes may be used as access devices and/or to build peripheral circuitry.

Abstract: Embodiments of the invention magnetic memory device, comprising: a plurality of magnetic memory cells, each comprising: a magnetic memory element capable of being flipped between two stable spin orientations under the influence of an applied magnetic field; and current-carrying conductors proximate the magnetic element to carry a current that induces said applied magnetic field, wherein the current-carrying conductors have a non-rectangular cross section; and a read circuit for reading data from the selected magnetic memory cells.

Abstract: In one embodiment, there is provided a method for programming a memory device having magnetoresistive memory elements as storage elements. The method is performed during fabrication of the memory device and may be used to realize a Magnetic Read Only Memory (MROM) device. In accordance with the method, during fabrication of a memory device comprising a plurality of magnetoresistive memory elements (MRME) e.g. a MTJs, the memory device is programmed by selectively controlling the presence or absence of the magnetoresistive element at each intersection of a word line (WL) and a bit line (BL) in the device.

Abstract: A magnetic memory cell in which a sensor is magnetically coupled to a magnetic media wherein the separation of the magnetic media from the sensor permits each to be magnetically optimized separate from the other, thus improving defect tolerance and minimizing the magnetic influence of neighboring cells in an array on one another. In an embodiment, the read circuitry is positioned so that no read current passes through the media during a read operation. In an alternative embodiment, processing is simplified but the read current is allowed to pass through the media.

Abstract: A solid state magnetic memory system and method disposes an array of magnetic media cells in an array on a substrate. In an exemplary embodiment, drive electronics are fabricated into the substrate through conventional CMOS processing in alignment with associated cells of the array. The magnetic media cells each include a magnetic media bit and a magnetoresistive or GMR stack for reading the state of the media bit. Addressing lines are juxtaposed with the media bits to permit programming and erasing of selected ones of the bits. In at least some embodiments, sector erase may be performed.

Abstract: Apparatuses and methods of an executable-in-place solid-state device are disclosed. In one embodiment, a solid-state device includes a flash memory coupled to a dynamic random access memory, the dynamic random access memory to store at least as much data as the flash memory; and a logic circuit coupled to the flash memory and the dynamic access memory to copy data from the flash memory to the dynamic random access memory on power up of a data processing system coupled to the solid-state device. The logic circuit is to minimize writes to the flash memory by using the dynamic access memory as a working memory during operation of the data processing system, and/or to block at least some sectors of at least one of the flash memory and the dynamic random access memory when the data processing system uses the working memory to conserve power usage of the solid-state device.