Abstract: A stacked chassis comprising multiple physical switch/router chassis operates without any special stacking hardware or stacking channels. Instead, a stacking LAG is installed between front-end switch ports on the stacked chassis. The chassis controllers negotiate a master, which controls operation of all chassis in the stack. A stacked-chassis-wide port numbering scheme is used to distribute information to all line cards in the system. Each line card processes the information to distill physical-chassis significant information for operation of that chassis in the stack.

Abstract: A data switching system is disclosed that allows for switching of packets through a plurality of top of rack switches utilizing a logical switching fabric that includes a local TOR switching fabric on a TOR switch and a Core switching fabric on a Core switch. A method of processing packets according to some embodiment can include receiving a packet from a source port into a top of rack switch, the source port being one of a plurality of ports on the top of rack switch, processing a packet header of the packet to determine a destination port; and switching the packet through a logical switching fabric that includes a local switch fabric on the top of rack switch and a Core switching fabric on a Core switch.

Abstract: A LAN includes a CORE switch linked to some number of TOR switches, and each of the TOR switches are linked directly to some number of host devices. Each of the switches in the LAN operate to process and transmit data frames they receive from neighboring LAN devices. Each TOR switch in the LAN builds and maintains a layer-2 forwarding table that is comprised of MAC address information learned from frames they receive from neighboring LAN devices. Selected ports/VLANs on some or all of the TOR devices are designated to be CORE/switch facing ports (CFP) or host facing ports (HFP). Each of the CFPs are configured to only learn the MAC address in unicast frames it receives and each of the HFPs can be configured to learn the MAC address of both unicast and multicast data frames provided the destination MAC address included in the unicast frame is known.

Abstract: A stacked chassis comprising multiple physical switch/router chassis operates without any special stacking hardware or stacking channels. Instead, a stacking LAG is installed between front-end switch ports on the stacked chassis. The chassis controllers negotiate a master, which controls operation of all chassis in the stack. A stacked-chassis-wide port numbering scheme is used to distribute information to all line cards in the system. Each line card processes the information to distill physical-chassis significant information for operation of that chassis in the stack.

Abstract: A data communication network includes a client device and multiple aggregation devices coupled to each other and the client via links within a link aggregation group (“LAG”) across the aggregation devices. The aggregation devices appear to the client as a single device coupled thereto, and operate in conjunction with each other by assigning at least one different identifier to each of the plurality of separate aggregation devices and storing information including the identifiers to association tables located on each of the aggregation devices. The multiple aggregation devices can be separate switches, and the LAG can include multiple ports across the switches, with a different identifier being assigned to each of the ports in the LAG. A virtual link trunk interface can couple aggregation devices, which can reconfigure communication paths thereacross with respect to the client device using the identifiers in the stored association tables when a LAG link fails.

Abstract: A financial market data network having a lowered overall latency includes communication interfaces, specialized switches having internal switching fabric, and feed handlers that all facilitate communications between financial exchanges and consumers of financial market data therefrom. A feed handler is situated within or proximate a specialized switch and is arranged to receive raw financial market data directly from financial exchanges without the data first traveling through any switching fabric. The feed handler is adapted to process the received raw financial market data into a normalized format before the normalized financial market data is ever routed through any switching fabric, prior to being sent to consumers. The communication interfaces can include I/O ports located on the specialized switches, and the feed handlers can include one or more computer processors or servers.

Abstract: Two network switches are configured in a stacked relationship to each other and include link aggregation sub-layer functionality. Switching tables are programmed on each switch with information used to forward packets ingressing to them over a redundant LAG that is identified in the switching table by a port that is a member of the redundant LAG.

Abstract: A LAN includes a router that is connected to two or more racks of servers and each of the servers can support a plurality of virtual machines. The router is configured to forward data packets based on IP destination addresses or based on destination MAC addresses and builds and maintains forwarding tables in support of data packet forwarding in the layer 3 and the layer 2 network environment. In support of layer 2 forwarding, the router builds and maintains an aggregated MAC switching table that is comprise of a subset of the table entries typically needed to switch packets to their destination, and in support of layer 3 forwarding, the router or switch builds and maintains an aggregated ARP forwarding table that is comprised of a subset of the table entries typically needed to forward packets to their destination.

Abstract: A stacked chassis comprising multiple physical switch/router chassis operates without any special stacking hardware or stacking channels. Instead, a stacking LAG is installed between front-end switch ports on the stacked chassis. The chassis controllers negotiate a master, which controls operation of all chassis in the stack. A stacked-chassis-wide port numbering scheme is used to distribute information to all line cards in the system. Each line card processes the information to distill physical-chassis significant information for operation of that chassis in the stack.

Abstract: A network switch is comprised of a control processor and one or more line cards. The control processor includes functionality to register interest with a hypervisor, operating in conjunction with a network host connected to the switch, in data object attributes maintained on the network host by the hypervisor. The hypervisor associated with the network host sends changes in the host attributes to the switch which the switch maintains in a listing of attributes. The switch traps and copies particular packets to the switch control processor where a provisioning function operates on the attribute information in the list with source information included in the packet header in order to configure a forwarding table on the line card.

Abstract: A packet network device, such as a router or switch, includes functionality that operates to receive network traffic, process the traffic as needed and to forward the traffic to its destination. Additionally, each router includes a weighted equal cost multipath routing function that operates to identify equal cost paths over which to forward the network traffic, to calculate a path weighting that is dependent upon the path bandwidth and to forward the traffic ingressing to it over each of the equal cost paths according to the calculated path weighting.

Abstract: A serial channel switch circuit and modular packet switch using the serial channel switch circuits are disclosed. The serial channel switch circuit has a reconfigurable table for internal logical-to-physical channel switch translation. Depending on the slot in which a card containing such a serial channel switch circuit is inserted in the modular packet switch, its serial channel switch circuit may receive a different set of reconfigurable table values that are specific to that location. A global set of logical channel values can be applied to each card, which performs logical-to-physical channel mapping according to its location in the modular packet switch. Other embodiments are also described and claimed.

Abstract: An autonomous system includes at least some packet network devices that are capable of operating in a virtual route aggregation environment and some packet network devices that are not capable of operating in a virtual route aggregation environment. The autonomous system includes at least one egress border router, at least one aggregation router and at least one intermediate router. The egress border router uses an interior border gateway protocol to distribute a label message to the other routers in the autonomous system, the label message including a next hop MAC address associated with either an external router or the egress border router. The egress border router and the intermediate router using information included in the label message to contrast layer 2 table entries and the aggregation router using information included in the label message to construct a layer 3 table entry.

Abstract: A stacked chassis comprising multiple physical switch/router chassis operates without any special stacking hardware or stacking channels. Instead, a stacking LAG is installed between front-end switch ports on the stacked chassis. The chassis controllers negotiate a master, which controls operation of all chassis in the stack. A stacked-chassis-wide port numbering scheme is used to distribute information to all line cards in the system. Each line card processes the information to distill physical-chassis significant information for operation of that chassis in the stack.

Abstract: A stacked chassis comprising multiple physical switch/router chassis operates without any special stacking hardware or stacking channels. Instead, a stacking LAG is installed between front-end switch ports on the stacked chassis. The chassis controllers negotiate a master, which controls operation of all chassis in the stack. A stacked-chassis-wide port numbering scheme is used to distribute information to all line cards in the system. Each line card processes the information to distill physical-chassis significant information for operation of that chassis in the stack.

Abstract: A stacked chassis comprising multiple physical switch/router chassis operates without any special stacking hardware or stacking channels. Instead, a stacking LAG is installed between front-end switch ports on the stacked chassis. The chassis controllers negotiate a master, which controls operation of all chassis in the stack. A stacked-chassis-wide port numbering scheme is used to distribute information to all line cards in the system. Each line card processes the information to distill physical-chassis significant information for operation of that chassis in the stack.

Abstract: An autonomous system includes at least some packet network devices that are capable of operating in a virtual route aggregation environment and some packet network devices that are not capable of operating in a virtual route aggregation environment. The autonomous system includes at least one egress border router, at least one aggregation router and at least one intermediate router. The egress border router uses an interior border gateway protocol to distribute a label message to the other routers in the autonomous system, the label message including a next hop MAC address associated with either an external router or the egress border router. The egress border router and the intermediate router using information included in the label message to contrast layer 2 table entries and the aggregation router using information included in the label message to construct a layer 3 table entry.

Abstract: In one embodiment of a network device, multiple packet sources contend for access to a packet processing pipeline. The packet processing pipeline tracks the usage of lookup resources by each of the multiple packet sources. When a packet source is detected to be using more than an acceptable allocation of the lookup resources, access to the packet processing pipeline for that source is limited or curtailed to bring that source back within an acceptable allocation of resources. This backpressure mechanism can be used to control sources that, although within a bandwidth limit, are submitting a packet type mix that is consuming unfair percentages of lookup resources in an oversubscribed system. Other embodiments are described and claimed.

Abstract: A packet network device includes a packet network processor memory system for storing information used to process and forward packets of information in and through the network device. The information is included in look-up tables whose entries can be mapped either horizontally or vertically into the memory system. In the event that the entries are mapped horizontally, a complete entry can be access at a single memory location and in the event that the entries are mapped vertically, the entries can be accessed at one or more memory locations.

Abstract: A network device such as a router or a switch is comprised of a control module and a plurality of physical line cards. The control module includes a control processor virtual machine, a plurality of route processing virtual machines and one or more instances of a line card virtual machine. The line card virtual machine operates to receive routing information base update information, to modify the routing information base according to the update information and to update each instance of a plurality of forwarding information bases included on each of the physical line cards.