Abstract: A floating point unit multiply logic in which a sticky bit is computed in parallel with partial product generation and reduction for three different rounding precisions and two different operand, ranges. Two sticky bits need to be calculated during the parallel operation because the result can be anywhere between 0 and 4 and it will not be known which is correct until after the result of the multiplication has been calculated. If the result is between 0 and 2, then a first sticky bit is generated. When the result is between 2 and 4, a second sticky bit is generated. It is not known which sticky bit is the correct one to use until the final addition is performed. Once the results of the final addition is known, the correct sticky bit is selected using a carry out from the adder, the overflow bit. If the overflow bit is a 1, then the first sticky bit is selected. If the overflow bit is a 0, then the second sticky bit is selected.

Abstract: An arithmetic logic for selectively multiplying either floating point numbers and unsigned integers or signed integers. A signed integer request signal has a first state indicating a floating point or unsigned integer operation and a second state indicating a signed integer operation. A multiplicand operand includes a most significant bit (MSB) of the multiplicand. A Booth encoder provides at an output of the Booth encoder a booth encoded set having a plurality of bits, including a most significant bit (MSB) of the booth encoded set. A partial product generator connected to the multiplicand operand and to the Booth encoder output generates a plurality of partial products. A carry save adder (CSA) connected to the partial product generator generates a sum vector and a carry vector. An exclusive OR has one input connected to the MSB of the Booth encoded set and another input connected to the MSB of the multiplicand. A 2:1 MUX is connected to the MSB of the Booth encoded set and to the exclusive OR.