Patents by Inventor Krishnan Kunjunny Kailas

Krishnan Kunjunny Kailas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for application-specific dynamic cache placement
    Publication number: 20080010413
    Abstract: One embodiment of the present method and apparatus for application-specific dynamic cache placement includes grouping sets of data in a cache memory system into two or more virtual partitions and processing a load/store instruction in accordance with the virtual partitions, where the load/store instruction specifies at least one of the virtual partitions to which the load/store instruction is assigned.
    Type: Application
    Filed: July 7, 2006
    Publication date: January 10, 2008
    Inventors: Krishnan Kunjunny Kailas, Rajiv Alazhath Ravindran, Zehra Sura
  • Method and apparatus for dynamic priority-based cache replacement
    Publication number: 20080010414
    Abstract: One embodiment of the present method and apparatus for dynamic priority-based cache replacement includes selectively assigning relative priority values to at least a subset of data items in the cache memory system, fetching a new data item to load into the cache memory system, the data item being associated with a priority value, and selecting an existing data item from the cache memory system to replace with the new data item, in accordance with the relative priority values and the-priority value of the new data item.
    Type: Application
    Filed: July 7, 2006
    Publication date: January 10, 2008
    Inventors: Krishnan Kunjunny Kailas, Rajiv Alazhath Ravindran, Zehra Sura
  • Method and system for modeling non-interlocked diversely bypassed exposed pipeline processors for static scheduling
    Publication number: 20040123072
    Abstract: A method (and structure) for modeling the timing of production and consumption of data produced and consumed by instructions on a processor using irregular pipeline and/or bypass structures, includes developing a port-based look-up table containing a delay compensation number for pairs of ports in at least one of an irregular pipeline and an irregular bypass structure. Each delay compensation number permits a calculation of an earliest/latest time an instruction can be scheduled.
    Type: Application
    Filed: December 18, 2002
    Publication date: June 24, 2004
    Applicant: International Business Machines Corporation
    Inventors: Krishnan Kunjunny Kailas, Ayal Zaks