Abstract: Embodiments of apparatuses, systems, articles, and methods related to a photovoltaic module monitoring system are disclosed. Other embodiments may be described and claimed.

Abstract: A radio transmitter and receiver arrangement includes a transmitter and a receiver. The transmitter generates an electromagnetic carrier that varies in frequency throughout a channel interval, and modulates the carrier with an information signal during the channel interval, whereby the carrier is modulated both in frequency and in accordance with the information signal during the channel interval. The receiver receives the carrier that is modulated both in frequency and in accordance with the information signal, generates a detection signal that varies in frequency throughout the channel interval, and mixes the carrier and the detection signal to recover the information signal.

Abstract: A radio transmitter and receiver arrangement includes a transmitter and a receiver. The transmitter generates an electromagnetic carrier that varies in frequency throughout a channel interval, and modulates the carrier with an information signal during the channel interval, whereby the carrier is modulated both in frequency and in accordance with the information signal during the channel interval. The receiver receives the carrier that is modulated both in frequency and in accordance with the information signal, generates a detection signal that varies in frequency throughout the channel interval, and mixes the carrier and the detection signal to recover the information signal.

Abstract: A radio transmitter and receiver arrangement includes a transmitter and a receiver. The transmitter generates an electromagnetic carrier that varies in frequency throughout a channel interval, and modulates the carrier with an information signal during the channel interval, whereby the carrier is modulated both in frequency and in accordance with the information signal during the channel interval. The receiver receives the carrier that is modulated both in frequency and in accordance with the information signal, generates a detection signal that varies in frequency throughout the channel interval, and mixes the carrier and the detection signal to recover the information signal.

Abstract: An isolation mechanism serves to isolate digital signal processor outputs from a dynamic random access memory controller upon the occurrence of a low power condition. The isolation prevents corruption of dynamic random access memory due to low power. The isolation mechanism receives inputs of a first low power indicator and a second low power indicator. The first low power indicator pulls low and the second low power indicator is forced high when a low power condition exists. One embodiment of the isolation mechanism includes a NAND gate connected to a first low power indicator signal and to a second low power indicator signal as inputs, a NOR gate connected with a NAND gate output as input, and a flip flop connected with a NOR gate output and the first low power indicator as inputs. The flip flop output is input to the NOR gate.

Abstract: A digital signal controller is provided having modular operation. Specifically, the digital signal controller includes a sequence control unit and a sequencer for producing a sequence of macro instructions and a sequence of micro instructions, respectively. Changes in the number or order of macro instructions may not require changes to the number and order of micro instructions and vice versa. As such, changes in macro instructions can occur by modifying the sequence control unit and possibly the decoder without necessarily changing the sequencer. Changes in the number and order of micro instructions requires changes in the sequencer and possibly the decoder without necessarily changing the sequence control unit.

Abstract: A frequency divider/counter circuit utilizing at clock and a clear signal to divide the clock by an odd value. A first adder receives the clock and the clear signal, and has a carry-in input, and generates an adder output and carry-out output. A second adder also receives the clock and the first adder cell carry-out output, and generates an adder output. A reset cell receives the clock and the clear signal, and has an input and generates a reset output. Logic receives selected adder outputs and generates a divider output when the odd value is reached, wherein the first adder receives the divider output as its carry-in input, the second adder receives the carry-out output of the first adder as its carry-in input and the reset output as its clear input, and the reset cell receives the divider output as its input.