Patents by Inventor Krishnan SRIDHAR

Krishnan SRIDHAR has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Resource allocation in a multi-processor system
    Patent number: 11714647
    Abstract: A system includes a memory-mapped register (MMR) associated with a claim logic circuit, a claim field for the MMR, a first firewall for a first address region, and a second firewall for a second address region. The MMR is associated with an address in the first address region and an address in the second address region. The first firewall is configured to pass a first write request for an address in the first address region to the claim logic circuit associated with the MMR. The claim logic circuit associated with the MMR is configured to grant or deny the first write request based on the claim field for the MMR. Further, the second firewall is configured to receive a second write request for an address in the second address region and grant or deny the second write request based on a permission level associated with the second write request.
    Type: Grant
    Filed: November 16, 2021
    Date of Patent: August 1, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Eric Robert Hansen, Krishnan Sridhar
  • 22 RESOURCE ALLOCATION IN A MULTI-PROCESSOR SYSTEM
    Publication number: 20220075621
    Abstract: A system includes a memory-mapped register (MMR) associated with a claim logic circuit, a claim field for the MMR, a first firewall for a first address region, and a second firewall for a second address region. The MMR is associated with an address in the first address region and an address in the second address region. The first firewall is configured to pass a first write request for an address in the first address region to the claim logic circuit associated with the MMR. The claim logic circuit associated with the MMR is configured to grant or deny the first write request based on the claim field for the MMR. Further, the second firewall is configured to receive a second write request for an address in the second address region and grant or deny the second write request based on a permission level associated with the second write request.
    Type: Application
    Filed: November 16, 2021
    Publication date: March 10, 2022
    Inventors: Eric Robert HANSEN, Krishnan SRIDHAR
  • Resource allocation in a multi-processor system
    Patent number: 11210095
    Abstract: A system includes a memory-mapped register (MMR) associated with a claim logic circuit, a claim field for the MMR, a first firewall for a first address region, and a second firewall for a second address region. The MMR is associated with an address in the first address region and an address in the second address region. The first firewall is configured to pass a first write request for an address in the first address region to the claim logic circuit associated with the MMR. The claim logic circuit associated with the MMR is configured to grant or deny the first write request based on the claim field for the MMR. Further, the second firewall is configured to receive a second write request for an address in the second address region and grant or deny the second write request based on a permission level associated with the second write request.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: December 28, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Eric Robert Hansen, Krishnan Sridhar
  • RESOURCE ALLOCATION IN A MULTI-PROCESSOR SYSTEM
    Publication number: 20200065099
    Abstract: A system includes a memory-mapped register (MMR) associated with a claim logic circuit, a claim field for the MMR, a first firewall for a first address region, and a second firewall for a second address region. The MMR is associated with an address in the first address region and an address in the second address region. The first firewall is configured to pass a first write request for an address in the first address region to the claim logic circuit associated with the MMR. The claim logic circuit associated with the MMR is configured to grant or deny the first write request based on the claim field for the MMR. Further, the second firewall is configured to receive a second write request for an address in the second address region and grant or deny the second write request based on a permission level associated with the second write request.
    Type: Application
    Filed: February 4, 2019
    Publication date: February 27, 2020
    Inventors: Eric Robert HANSEN, Krishnan SRIDHAR