Patents by Inventor Krishnan Subramoniam

Krishnan Subramoniam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7339628
    Abstract: Video decoder systems in which both the analog-to-digital converter and the composite decoder are driven by the stable sample clock, such as a crystal source. The outputs of the composite decoder are provided to a source rate converter, having an output that is provided to a digital output formatter. The digital output formatter is driven by the output clock, which may be locked to the source clock if desired. The output clock is developed by a clock generator which may be one of several different types, including a fractional N synthesizer, a direct digital synthesizer or a puncture clock.
    Type: Grant
    Filed: October 13, 2004
    Date of Patent: March 4, 2008
    Assignee: Cirrus Logic, Inc.
    Inventors: Daniel Gudmondson, John L. Melanson, Rahul Singh, James A. Antone, Ahsan Habib Chowdhury, Krishnan Subramoniam
  • Patent number: 7224756
    Abstract: A clock generator system and method for providing and operating a codes with a clock signal at a desired operational rate are disclosed. The clock generator system also has a phase-locked loop circuit. The clock generator system determines whether an available clock signal within a circuit environment of the codec has a desired clock rate. If the available clock signal has the desired clock rate, the clock generator system supplies and operates the codec with the available clock signal. If the available clock signal does not have the desired clock rate, the phase-locked loop circuit generates from the available clock signal a desired clock signal having the desired clock rate and supplies and operates the codec with the desired clock signal.
    Type: Grant
    Filed: May 13, 2002
    Date of Patent: May 29, 2007
    Assignee: Cirrus Logic, Inc.
    Inventors: Krishnan Subramoniam, Jens Puchert, Anand Venkitachalam, Brian K. Straup, John L. Melanson
  • Patent number: 7162029
    Abstract: A gain or input volume controller and method includes a modified R2R ladder network having a number of R2R branches, switches coupled respectively to the R2R branches, and a switch controller for respectively controlling the switches to control and provide an overall gain value for a signal. The switch controller further includes a mapper for mapping a gain control signal to the switches wherein the gain control signal respectively activates or deactivates the switches. A fine gain control stage provides a fine gain control of the overall gain value. A coarse gain control stage is coupled to the fine gain control stage. The coarse gain control stage includes the modified R2R ladder network and provides a coarse gain control of the overall gain value.
    Type: Grant
    Filed: May 29, 2003
    Date of Patent: January 9, 2007
    Assignee: Cirrus Logic, Inc.
    Inventors: Manoj Soman, Krishnan Subramoniam, Hua Hong, Rajendra Datar, John Laurence Melanson
  • Publication number: 20060078054
    Abstract: Video decoder systems in which both the analog-to-digital converter and the composite decoder are driven by the stable sample clock, such as a crystal source. The outputs of the composite decoder are provided to a source rate converter, having an output that is provided to a digital output formatter. The digital output formatter is driven by the output clock, which may be locked to the source clock if desired. The output clock is developed by a clock generator which may be one of several different types, including a fractional N synthesizer, a direct digital synthesizer or a puncture clock.
    Type: Application
    Filed: October 13, 2004
    Publication date: April 13, 2006
    Inventors: Daniel Gudmundson, John Melanson, Rahul Singh, James Antone, Ahsan Chowdhury, Krishnan Subramoniam
  • Patent number: 7019677
    Abstract: A current steering digital to analog converter includes a current source for selectively providing a selected amount of current to an output in response to input data. The current source includes a selected number of sub-current sources for selectively providing fractions of the selected amount of current to the output. Compensation current sources each provide a selected amount of compensation current to the output. Compensation control circuitry, in response to the input data, selectively activates and de-activates selected ones of the sub-current sources and the compensation current sources to provide current compensation at the output.
    Type: Grant
    Filed: September 8, 2004
    Date of Patent: March 28, 2006
    Assignee: Cirrus Logic, Inc.
    Inventors: Manoj Shridhar Soman, Krishnan Subramoniam, Rajendra Datar
  • Publication number: 20060044468
    Abstract: A single-chip video decoder includes a primary data path for capturing and slicing vertical blanking interval information carried by a primary channel of video data received by a video decoder. Power control circuitry is operable during an inactive period of the video decoder to activate the primary data path during vertical blanking intervals of the received primary channel of video data for capturing and slicing the vertical blanking interval data; and to deactivate the primary data path between the vertical blanking interval and a subsequent vertical blanking interval of the received primary channel of video data to reduce power consumption. According to further inventive concepts, analog and/or digital circuitry which is unnecessary for capturing and slicing the vertical blanking information, including data paths processing secondary channels of video data, is deactivated during substantially the entire inactive period of the video decoder.
    Type: Application
    Filed: January 24, 2005
    Publication date: March 2, 2006
    Applicant: Cirrus Logic, Inc.
    Inventors: Ahsan Chowdhury, James Antone, Krishnan Subramoniam
  • Publication number: 20040240918
    Abstract: A gain or input volume controller and method includes a modified R2R ladder network having a number of R2R branches, switches coupled respectively to the R2R branches, and a switch controller for respectively controlling the switches to control and provide an overall gain value for a signal. The switch controller further includes a mapper for mapping a gain control signal to the switches wherein the gain control signal respectively activates or deactivates the switches. A fine gain control stage provides a fine gain control of the overall gain value. A coarse gain control stage is coupled to the fine gain control stage. The coarse gain control stage includes the modified R2R ladder network and provides a coarse gain control of the overall gain value.
    Type: Application
    Filed: May 29, 2003
    Publication date: December 2, 2004
    Inventors: Manoj Soman, Krishnan Subramoniam, Hua Hong, Rajendra Datar, John Melanson
  • Patent number: 6642863
    Abstract: A method of performing sample rate conversion in a data converter operating from an oversampling clock corresponding to a native sample rate and a native oversampling factor. A virtual sample rate and a virtual oversampling factor are selected proportional to the native sample rate and the native oversampling factor. A data stream having a data sample rate is sampled by the virtual oversampling factor. The data stream is also resampled with a resampling ratio approximating a ratio of the data sample rate to the virtual sample rate.
    Type: Grant
    Filed: March 11, 2002
    Date of Patent: November 4, 2003
    Assignee: Cirrus Logic, Inc.
    Inventors: Anand Venkitachalam, Dylan Alexander Hester, Brian Frank Bounds, Rajendra Datar, Krishnan Subramoniam
  • Patent number: 6642876
    Abstract: A system and method of operating a codec in an operational mode are disclosed. The codec is operated in a digital centric mode. The digital centric mode involves the following: An analog mixer of the codec first mixes analog signals, if any, to produce a mixed analog signal. An analog-to-digital converter converts the mixed analog signal into a converted digital signal. A digital mixer mixes the converted digital signal with digital signals that are otherwise generally unavailable as analog signals to the codec without additional conversions to produce a mixed digital signal. A digital-to-analog converter converts the mixed digital signal into a mixed analog signal. A digital processor may perform digital effects processing on the mixed digital signal to add digital effects to the mixed digital signal. The codec is still able to alternatively operate in an analog centric mode, a host processing mode, or a multi-channel mode.
    Type: Grant
    Filed: July 26, 2002
    Date of Patent: November 4, 2003
    Assignee: Cirrus Logic, Inc.
    Inventors: Krishnan Subramoniam, Jens Puchert, Brian K. Straup
  • Patent number: 6608572
    Abstract: An integrated analog to digital and sample rate converter 206 includes sampling circuitry 207 for receiving an analog signal and generating a single or multibit stream of digital signals at a first rate. A leaky integrator filter 208 removes quantization noise from the stream of samples such that resampling can be carried out. Circuitry 209/210 resamples the filtered stream of samples output from leaky integrator filter 208 to generate an output stream of samples at a second rate.
    Type: Grant
    Filed: August 31, 2001
    Date of Patent: August 19, 2003
    Assignee: Cirrus Logic, Inc.
    Inventors: Anand Venkitachalam, Joe Welser, Manoj Soman, Krishnan Subramoniam
  • Publication number: 20030067402
    Abstract: A system and method of operating a codec in an operational mode are disclosed. The codec is operated in a digital centric mode. The digital centric mode involves the following: An analog mixer of the codec first mixes analog signals, if any, to produce a mixed analog signal. An analog-to-digital converter converts the mixed analog signal into a converted digital signal. A digital mixer mixes the converted digital signal with digital signals that are otherwise generally unavailable as analog signals to the codec without additional conversions to produce a mixed digital signal. A digital-to-analog converter converts the mixed digital signal into a mixed analog signal. A digital processor may perform digital effects processing on the mixed digital signal to add digital effects to the mixed digital signal. The codec is still able to alternatively operate in an analog centric mode, a host processing mode, or a multi-channel mode.
    Type: Application
    Filed: July 26, 2002
    Publication date: April 10, 2003
    Inventors: Krishnan Subramoniam, Jens Puchert, Brian K. Straup
  • Patent number: 6542094
    Abstract: A sample rate converter for converting a data stream having a first base sampling frequency to a data stream having a second base sampling frequency. Up-sampling circuitry receives first oversampled data having a first oversampling ratio with respects to the first base frequency and outputs second oversampled data having a second oversampling ratio with respects to the first base sampling frequency. Resampling circuitry resamples the second oversampled data by a resampling frequency ratio of integers representing a ratio of the first and second base frequencies and generates third oversampled data having the second oversampling ratio with respects to the second base frequency. Down-sampling circuitry then down-samples the third oversampled data and generates fourth oversampled data having the first oversampling ratio with respects to the second base frequency.
    Type: Grant
    Filed: March 4, 2002
    Date of Patent: April 1, 2003
    Assignee: Cirrus Logic, Inc.
    Inventors: Anad Venkitachalam, Rajendra Datar, Krishnan Subramoniam
  • Publication number: 20030026368
    Abstract: A clock generator system and method for providing and operating a codes with a clock signal at a desired operational rate are disclosed. The clock generator system also has a phase-locked loop circuit. The clock generator system determines whether an available clock signal within a circuit environment of the codec has a desired clock rate. If the available clock signal has the desired clock rate, the clock generator system supplies and operates the codec with the available clock signal. If the available clock signal does not have the desired clock rate, the phase-locked loop circuit generates from the available clock signal a desired clock signal having the desired clock rate and supplies and operates the codec with the desired clock signal.
    Type: Application
    Filed: May 13, 2002
    Publication date: February 6, 2003
    Inventors: Krishnan Subramoniam, Jens Puchert, Anand Venkitachalam, Brian Straup, John Melanson
  • Patent number: 6489901
    Abstract: A sample rate converter 210, 209 includes a filter 210 for processing digital data in response to a clock controlled by a clock enable signal, the filter 210 receiving the digital data at a first sampling rate and outputting digital data at a second sampling rate. Resampler circuitry 209 generates first selected periods of the clock enable signal having a first duty cycle approximating a ratio between the first sampling rate and the second sampling rate. Selectively, selected periods of the clock enable signal are generated having a second duty cycle for minimizing an error accumulated over the first selected periods of the clock enable signal.
    Type: Grant
    Filed: August 31, 2001
    Date of Patent: December 3, 2002
    Assignee: Cirrus Logic, Inc.
    Inventors: Anand Venkitachalam, Dylan Hester, Joe Welser, Rajendra Datar, Krishnan Subramoniam