Patents by Inventor Krishnan Sugavanam

Krishnan Sugavanam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • USER AUTHENTICATION BASED ON PERIODIC SAMPLING OF LOCATION COORDINATES
    Publication number: 20240056455
    Abstract: According to one embodiment, a method, computer system, and computer program product for user authentication. The embodiment may include receiving, from a first device, multiple location coordinates of the first device. The embodiment may include storing, on a second device, a second moving window comprising last n location coordinates of the multiple location coordinates. The embodiment may include receiving, from the first device, a request to access the second device, wherein the request comprises log-in credentials and a first hash value. The embodiment may include computing, on the second device, a second hash value based on the second moving window. The embodiment may include verifying the log-in credentials. The embodiment may include comparing the first hash value and the second hash value. In response to the first and the second hash values being equal, and the log-in credentials being verified, the embodiment may include granting access.
    Type: Application
    Filed: April 19, 2023
    Publication date: February 15, 2024
    Inventors: Krishnan Sugavanam, ARIS GKOULALAS-DIVANIS, Sophie Batchelder, Uri Kartoun
  • Autonomous webpage content summation
    Patent number: 11860946
    Abstract: A computer-implemented method includes: receiving, by a computing device, text extracted from a webpage in a browser and a Uniform Resource Locator (URL) of a linked webpage associated with the text; generating, by the computing device, questions based on the text; retrieving, by the computing device, content of the linked webpage using the URL; generating, by the computing device, answers to the questions using the retrieved content; and returning, by the computing device, the questions and the answers to the browser such that the browser displays the questions and the answers in the webpage.
    Type: Grant
    Filed: January 11, 2022
    Date of Patent: January 2, 2024
    Assignee: KYNDRYL, INC.
    Inventors: Michael Seth Silverstein, Zachary A. Silverstein, Jayanth Krishnan, Krishnan Sugavanam
  • PUSH NOTIFICATION PERSISTENCE MANAGEMENT
    Publication number: 20230283688
    Abstract: A computer-implemented method including: displaying, by a mobile device, a push notification from an application of the mobile device; determining, by the mobile device, an associated notification parameter for the push notification; receiving, by the mobile device, a user input by a user of the mobile device; determining, by the mobile device, the user input indicates interest in the push notification; and maintaining, by the mobile device, presence of the push notification on a display of the mobile device based on determining the user input indicates interest in the push notification and the associated notification parameter.
    Type: Application
    Filed: March 3, 2022
    Publication date: September 7, 2023
    Inventors: Michael Seth SILVERSTEIN, Zachary A. SILVERSTEIN, Jayanth KRISHNAN, Krishnan SUGAVANAM
  • AUTONOMOUS WEBPAGE CONTENT SUMMATION
    Publication number: 20230222164
    Abstract: A computer-implemented method includes: receiving, by a computing device, text extracted from a webpage in a browser and a Uniform Resource Locator (URL) of a linked webpage associated with the text; generating, by the computing device, questions based on the text; retrieving, by the computing device, content of the linked webpage using the URL; generating, by the computing device, answers to the questions using the retrieved content; and returning, by the computing device, the questions and the answers to the browser such that the browser displays the questions and the answers in the webpage.
    Type: Application
    Filed: January 11, 2022
    Publication date: July 13, 2023
    Inventors: Michael Seth Silverstein, Zachary A. Silverstein, Jayanth Krishnan, Krishnan Sugavanam
  • Methods and systems for creating root-of-trust for computing system components
    Patent number: 11675602
    Abstract: Embodiments for managing a computing system are provided. A Root-of-Trust (RoT) device within the computing system is caused to boot. The computing system includes at least one peripheral device, and the RoT device is in operable communication with the at least one peripheral device and a management server. The at least one peripheral device is caused to at least partially boot. The RoT device is caused to retrieve a firmware image associated with the at least one peripheral device from the management server. The at least one peripheral device is caused to reboot utilizing the firmware image.
    Type: Grant
    Filed: July 28, 2021
    Date of Patent: June 13, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sandhya Koteshwara, Krishnan Sugavanam, Dong Chen
  • METHOD FOR CONCEALING SENSITIVE MAIL RETURN ADDRESSES
    Publication number: 20230094317
    Abstract: A computer-implemented method for obfuscating sensitive information associated with mail delivery is disclosed. The computer-implemented method includes identifying that a piece of mail directed towards a potential recipient includes a particular type of sensitive information. The computer-implemented method further includes selecting a mail obfuscation policy for the particular type of sensitive information based on the particular type of sensitive information. The computer-implemented method further includes performing an obfuscation action with respect to the particular type of sensitive information based on the selected mail obfuscation policy.
    Type: Application
    Filed: September 27, 2021
    Publication date: March 30, 2023
    Inventors: Uri Kartoun, Aris Gkoulalas-Divanis, Sophie Batchelder, Krishnan Sugavanam
  • METHODS AND SYSTEMS FOR CREATING ROOT-OF-TRUST FOR COMPUTING SYSTEM COMPONENTS
    Publication number: 20230033667
    Abstract: Embodiments for managing a computing system are provided. A Root-of-Trust (RoT) device within the computing system is caused to boot. The computing system includes at least one peripheral device, and the RoT device is in operable communication with the at least one peripheral device and a management server. The at least one peripheral device is caused to at least partially boot. The RoT device is caused to retrieve a firmware image associated with the at least one peripheral device from the management server. The at least one peripheral device is caused to reboot utilizing the firmware image.
    Type: Application
    Filed: July 28, 2021
    Publication date: February 2, 2023
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sandhya KOTESHWARA, Krishnan SUGAVANAM, Dong CHEN
  • ORDERING COLLABORATIVE ACTIONS IN A GRAPHICAL USER INTERFACE
    Publication number: 20220413690
    Abstract: A computer-implemented method for organizing tasks presented on a graphical user interface of a computer hardware system for a user includes the following operations. An electronic message associated with a collaborative messaging application executing with the computer hardware system is received. A first collaboration having one or more collaborative tasks is identified from the electronic message. A need-for-action, a time-to-act, and a time-to-complete are determined for the first collaboration. A moving average for the first collaboration is adjusted based upon the need-for-action, the time-to-action, and a time-to-complete. The presentation of the first collaboration within the graphical user interface is altered based upon the moving average.
    Type: Application
    Filed: June 24, 2021
    Publication date: December 29, 2022
    Inventors: Keith Kaplan, Jayanth Krishnan, Paul R. Bastide, Krishnan Sugavanam
  • CONTROLLING A DISPLAY BASED ON A PROXIMITY OF A PORTABLE DEVICE
    Publication number: 20220269830
    Abstract: A method secures a computer display. One or more processors detect whether there is a presence of an authorized portable device proximate to the computer display. Based on what the processor(s) detect, the processor(s) apply a rule, which is based on one or more portable devices being proximate to the computer display, to selectively continue or end a current session on the computer display.
    Type: Application
    Filed: February 24, 2021
    Publication date: August 25, 2022
    Inventors: URI KARTOUN, KRISHNAN SUGAVANAM, JAYANTH KRISHNAN, ARIS GKOULALAS-DIVANIS
  • Access control management of baseboard management controller peripherals
    Patent number: 11409918
    Abstract: Described is a baseboard management controller (BMC). The BMC comprises a BMC flash storage storing firmware and an access permission table. The access permission table defines an access control policy for access requests to peripherals communicatively coupled to the BMC. The BMC further comprises an access control chip comprising one or more processors and a write-once memory. The write-once memory stores a copy of the access permission table. The access control chip is configured to manage access to the peripherals using the access permission table.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: August 9, 2022
    Assignee: International Business Machines Corporation
    Inventors: Krishnan Sugavanam, Sandhya Koteshwara, Dong Chen
  • Multi-petascale highly efficient parallel supercomputer
    Patent number: 9971713
    Abstract: A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaflop-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC). The ASIC nodes are interconnected by a five dimensional torus network that optimally maximize the throughput of packet communications between nodes and minimize latency. The network implements collective network and a global asynchronous network that provides global barrier and notification functions. Integrated in the node design include a list-based prefetcher. The memory system implements transaction memory, thread level speculation, and multiversioning cache that improves soft error rate at the same time and supports DMA functionality allowing for parallel processing message-passing.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: May 15, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sameh Asaad, Ralph E. Bellofatto, Michael A. Blocksome, Matthias A. Blumrich, Peter Boyle, Jose R. Brunheroto, Dong Chen, Chen-Yong Cher, George L. Chiu, Norman Christ, Paul W. Coteus, Kristan D. Davis, Gabor J. Dozsa, Alexandre E. Eichenberger, Noel A. Eisley, Matthew R. Ellavsky, Kahn C. Evans, Bruce M. Fleischer, Thomas W. Fox, Alan Gara, Mark E. Giampapa, Thomas M. Gooding, Michael K. Gschwind, John A. Gunnels, Shawn A. Hall, Rudolf A. Haring, Philip Heidelberger, Todd A. Inglett, Brant L. Knudson, Gerard V. Kopcsay, Sameer Kumar, Amith R. Mamidala, James A. Marcella, Mark G. Megerian, Douglas R. Miller, Samuel J. Miller, Adam J. Muff, Michael B. Mundy, John K. O'Brien, Kathryn M. O'Brien, Martin Ohmacht, Jeffrey J. Parker, Ruth J. Poole, Joseph D. Ratterman, Valentina Salapura, David L. Satterfield, Robert M. Senger, Burkhard Steinmacher-Burow, William M. Stockdell, Craig B. Stunkel, Krishnan Sugavanam, Yutaka Sugawara, Todd E. Takken, Barry M. Trager, James L. Van Oosten, Charles D. Wait, Robert E. Walkup, Alfred T. Watson, Robert W. Wisniewski, Peng Wu
  • Local bypass for in memory computing
    Patent number: 9390038
    Abstract: Embodiments include a method for bypassing data in an active memory device. The method includes a requestor determining a number of transfers to a grantor that have not been communicated to the grantor, requesting to the interconnect network that the bypass path be used for the transfers based on the number of transfers meeting a threshold and communicating the transfers via the bypass path to the grantor based on the request, the interconnect network granting control of the grantor in response to the request. The method also includes the interconnect network requesting control of the grantor based on an event and communicating delayed transfers via the interconnect network from other requestors, the delayed transfers being delayed due to the grantor being previously controlled by the requestor, the communicating based on the control of the grantor being changed back to the interconnect network.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: July 12, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bruce M. Fleischer, Thomas W. Fox, Hans M. Jacobson, Ravi Nair, Martin Ohmacht, Krishnan Sugavanam
  • Local bypass in memory computing
    Patent number: 9298654
    Abstract: Embodiments include a method for bypassing data in an active memory device. The method includes a requestor determining a number of transfers to a grantor that have not been communicated to the grantor, requesting to the interconnect network that the bypass path be used for the transfers based on the number of transfers meeting a threshold and communicating the transfers via the bypass path to the grantor based on the request, the interconnect network granting control of the grantor in response to the request. The method also includes the interconnect network requesting control of the grantor based on an event and communicating delayed transfers via the interconnect network from other requestors, the delayed transfers being delayed due to the grantor being previously controlled by the requestor, the communicating based on the control of the grantor being changed back to the interconnect network.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 29, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bruce M. Fleischer, Thomas W. Fox, Hans M. Jacobson, Ravi Nair, Martin Ohmacht, Krishnan Sugavanam
  • MULTI-PETASCALE HIGHLY EFFICIENT PARALLEL SUPERCOMPUTER
    Publication number: 20160011996
    Abstract: A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaflop-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC). The ASIC nodes are interconnected by a five dimensional torus network that optimally maximize the throughput of packet communications between nodes and minimize latency. The network implements collective network and a global asynchronous network that provides global barrier and notification functions. Integrated in the node design include a list-based prefetcher. The memory system implements transaction memory, thread level speculation, and multiversioning cache that improves soft error rate at the same time and supports DMA functionality allowing for parallel processing message-passing.
    Type: Application
    Filed: April 30, 2015
    Publication date: January 14, 2016
    Inventors: Sameh Asaad, Ralph E. Bellofatto, Michael A. Blocksome, Matthias A. Blumrich, Peter Boyle, Jose R. Brunheroto, Dong Chen, Chen-Yong Cher, George L. Chiu, Norman Christ, Paul W. Coteus, Kristan D. Davis, Gabor J. Dozsa, Alexandre E. Eichenberger, Noel A. Eisley, Matthew R. Ellavsky, Kahn C. Evans, Bruce M. Fleischer, Thomas W. Fox, Alan Gara, Mark E. Giampapa, Thomas M. Gooding, Michael K. Gschwind, John A. Gunnels, Shawn A. Hall, Rudolf A. Haring, Philip Heidelberger, Todd A. Inglett, Brant L. Knudson, Gerard V. Kopcsay, Sameer Kumar, Amith R. Mamidala, James A. Marcella, Mark G. Megerian, Douglas R. Miller, Samuel J. Miller, Adam J. Muff, Michael B. Mundy, John K. O'Brien, Kathryn M. O'Brien, Martin Ohmacht, Jeffrey J. Parker, Ruth J. Poole, Joseph D. Ratterman, Valentina Salapura, David L. Satterfield, Robert M. Senger, Burkhard Steinmacher-Burow, William M. Stockdell, Craig B. Stunkel, Krishnan Sugavanam, Yutaka Sugawara, Todd E. Takken, Barry M. Trager, James L. Van Oosten, Charles D. Wait, Robert E. Walkup, Alfred T. Watson, Robert W. Wisniewski, Peng Wu
  • Multi-petascale highly efficient parallel supercomputer
    Patent number: 9081501
    Abstract: A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC).
    Type: Grant
    Filed: January 10, 2011
    Date of Patent: July 14, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sameh Asaad, Ralph E. Bellofatto, Michael A. Blocksome, Matthias A. Blumrich, Peter Boyle, Jose R. Brunheroto, Dong Chen, Chen-Yong Cher, George L. Chiu, Norman Christ, Paul W. Coteus, Kristan D. Davis, Gabor J. Dozsa, Alexandre E. Eichenberger, Noel A. Eisley, Matthew R. Ellavsky, Kahn C. Evans, Bruce M. Fleischer, Thomas W. Fox, Alan Gara, Mark E. Giampapa, Thomas M. Gooding, Michael K. Gschwind, John A. Gunnels, Shawn A. Hall, Rudolf A. Haring, Philip Heidelberger, Todd A. Inglett, Brant L. Knudson, Gerard V. Kopcsay, Sameer Kumar, Amith R. Mamidala, James A. Marcella, Mark G. Megerian, Douglas R. Miller, Samuel J. Miller, Adam J. Muff, Michael B. Mundy, John K. O'Brien, Kathryn M. O'Brien, Martin Ohmacht, Jeffrey J. Parker, Ruth J. Poole, Joseph D. Ratterman, Valentina Salapura, David L. Satterfield, Robert M. Senger, Brian Smith, Burkhard Steinmacher-Burow, William M. Stockdell, Craig B. Stunkel, Krishnan Sugavanam, Yutaka Sugawara, Todd E. Takken, Barry M. Trager, James L. Van Oosten, Charles D. Wait, Robert E. Walkup, Alfred T. Watson, Robert W. Wisniewski, Peng Wu
  • Testing and operating a multiprocessor chip with processor redundancy
    Patent number: 8868975
    Abstract: A system and method for improving the yield rate of a multiprocessor semiconductor chip that includes primary processor cores and one or more redundant processor cores. A first tester conducts a first test on one or more processor cores, and encodes results of the first test in an on-chip non-volatile memory. A second tester conducts a second test on the processor cores, and encodes results of the second test in an external non-volatile storage device. An override bit of a multiplexer is set if a processor core fails the second test. In response to the override bit, the multiplexer selects a physical-to-logical mapping of processor IDs according to one of: the encoded results in the memory device or the encoded results in the external storage device. On-chip logic configures the processor cores according to the selected physical-to-logical mapping.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: October 21, 2014
    Assignee: International Business Machines Corporation
    Inventors: Ralph E. Bellofatto, Steven M. Douskey, Rudolf A. Haring, Moyra K. McManus, Martin Ohmacht, Dietmar Schmunkamp, Krishnan Sugavanam, Bryan J. Weatherford
  • LOCAL BYPASS FOR IN MEMORY COMPUTING
    Publication number: 20140281084
    Abstract: Embodiments include a method for bypassing data in an active memory device. The method includes a requestor determining a number of transfers to a grantor that have not been communicated to the grantor, requesting to the interconnect network that the bypass path be used for the transfers based on the number of transfers meeting a threshold and communicating the transfers via the bypass path to the grantor based on the request, the interconnect network granting control of the grantor in response to the request. The method also includes the interconnect network requesting control of the grantor based on an event and communicating delayed transfers via the interconnect network from other requestors, the delayed transfers being delayed due to the grantor being previously controlled by the requestor, the communicating based on the control of the grantor being changed back to the interconnect network.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bruce M. Fleischer, Thomas W. Fox, Hans M. Jacobson, Ravi Nair, Martin Ohmacht, Krishnan Sugavanam
  • LOCAL BYPASS FOR IN MEMORY COMPUTING
    Publication number: 20140281100
    Abstract: Embodiments include a method for bypassing data in an active memory device. The method includes a requestor determining a number of transfers to a grantor that have not been communicated to the grantor, requesting to the interconnect network that the bypass path be used for the transfers based on the number of transfers meeting a threshold and communicating the transfers via the bypass path to the grantor based on the request, the interconnect network granting control of the grantor in response to the request. The method also includes the interconnect network requesting control of the grantor based on an event and communicating delayed transfers via the interconnect network from other requestors, the delayed transfers being delayed due to the grantor being previously controlled by the requestor, the communicating based on the control of the grantor being changed back to the interconnect network.
    Type: Application
    Filed: August 14, 2013
    Publication date: September 18, 2014
    Applicant: International Business Machines Corporation
    Inventors: Bruce M. Fleischer, Thomas W. Fox, Hans M. Jacobson, Ravi Nair, Martin Ohmacht, Krishnan Sugavanam
  • List based prefetch
    Patent number: 8806141
    Abstract: A list prefetch engine improves a performance of a parallel computing system. The list prefetch engine receives a current cache miss address. The list prefetch engine evaluates whether the current cache miss address is valid. If the current cache miss address is valid, the list prefetch engine compares the current cache miss address and a list address. A list address represents an address in a list. A list describes an arbitrary sequence of prior cache miss addresses. The prefetch engine prefetches data according to the list, if there is a match between the current cache miss address and the list address.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: August 12, 2014
    Assignee: International Business Machines Corporation
    Inventors: Peter Boyle, Norman Christ, Alan Gara, Changhoan Kim, Robert Mawhinney, Martin Ohmacht, Krishnan Sugavanam
  • Pausing and activating thread state upon pin assertion by external logic monitoring polling loop exit time condition
    Patent number: 8447960
    Abstract: A system and method for enhancing performance of a computer which includes a computer system including a data storage device. The computer system includes a program stored in the data storage device and steps of the program are executed by a processer. The processor processes instructions from the program. A wait state in the processor waits for receiving specified data. A thread in the processor has a pause state wherein the processor waits for specified data. A pin in the processor initiates a return to an active state from the pause state for the thread. A logic circuit is external to the processor, and the logic circuit is configured to detect a specified condition. The pin initiates a return to the active state of the thread when the specified condition is detected using the logic circuit.
    Type: Grant
    Filed: January 8, 2010
    Date of Patent: May 21, 2013
    Assignee: International Business Machines Corporation
    Inventors: Dong Chen, Mark Giampapa, Philip Heidelberger, Martin Ohmacht, David L. Satterfield, Burkhard Steinmacher-Burow, Krishnan Sugavanam