Patents by Inventor Krishnan V. Ramani

Krishnan V. Ramani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11048506
    Abstract: A system and method for tracking stores and loads to reduce load latency when forming the same memory address by bypassing a load store unit within an execution unit is disclosed. Store-load pairs which have a strong history of store-to-load forwarding are identified. Once identified, the load is memory renamed to the register stored by the store. The memory dependency predictor may also be used to detect loads that are dependent on a store but cannot be renamed. In such a configuration, the dependence is signaled to the load store unit and the load store unit uses the information to issue the load after the identified store has its physical address.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: June 29, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Krishnan V. Ramani, Kai Troester, Frank C. Galloway, David N. Suggs, Michael D. Achenbach, Betty Ann McDaniel, Marius Evers
  • Patent number: 10990393
    Abstract: Address-based filtering for load/store speculation includes maintaining a filtering table including table entries associated with ranges of addresses; in response to receiving an ordering check triggering transaction, querying the filtering table using a target address of the ordering check triggering transaction to determine if an instruction dependent upon the ordering check triggering transaction has previously been generated a physical address; and in response to determining that the filtering table lacks an indication that the instruction dependent upon the ordering check triggering transaction has previously been generated a physical address, bypassing a lookup operation in an ordering violation memory structure to determine whether the instruction dependent upon the ordering check triggering transaction is currently in-flight.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: April 27, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: John Kalamatianos, Krishnan V. Ramani, Susumu Mashimo
  • Publication number: 20210117203
    Abstract: Speculative execution using a page-level tracked load order queue includes: determining that a first load instruction targets a determined memory region; and in response to the first load instruction targeting the determined memory region, adding an entry to a page-level tracked load order queue instead of a load order queue, where the entry indicates a page address of a target of the first load instruction.
    Type: Application
    Filed: October 21, 2019
    Publication date: April 22, 2021
    Inventor: KRISHNAN V. RAMANI
  • Publication number: 20210117195
    Abstract: Address-based filtering for load/store speculation includes maintaining a filtering table including table entries associated with ranges of addresses; in response to receiving an ordering check triggering transaction, querying the filtering table using a target address of the ordering check triggering transaction to determine if an instruction dependent upon the ordering check triggering transaction has previously been generated a physical address; and in response to determining that the filtering table lacks an indication that the instruction dependent upon the ordering check triggering transaction has previously been generated a physical address, bypassing a lookup operation in an ordering violation memory structure to determine whether the instruction dependent upon the ordering check triggering transaction is currently in-flight.
    Type: Application
    Filed: October 21, 2019
    Publication date: April 22, 2021
    Inventors: JOHN KALAMATIANOS, KRISHNAN V. RAMANI, SUSUMU MASHIMO
  • Patent number: 10949201
    Abstract: A processor and method for handling lock instructions identifies which of a plurality of older store instructions relative to a current lock instruction are able to be locked. The method and processor lock the identified older store instructions as an atomic group with the current lock instruction. The method and processor negatively acknowledge probes until all of the older store instructions in the atomic group have written to cache memory. In some implementations, an atomic grouping unit issues an indication to lock identified older store instructions that are retired and lockable, and in some implementations, also issues an indication to lock older stores that are determined to be lockable that are non-retired.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: March 16, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Scott Thomas Bingham, Marius Evers, Krishnan V. Ramani, Thomas Kunjan
  • Publication number: 20200319889
    Abstract: A technique for speculatively executing load-dependent instructions includes detecting that a memory ordering consistency queue is full for a completed load instruction. The technique also includes storing data loaded by the completed load instruction into a storage location for storing data when the memory ordering consistency queue is full. The technique further includes speculatively executing instructions that are dependent on the completed load instruction. The technique also includes in response to a slot becoming available in the memory ordering consistency queue, replaying the load instruction. The technique further includes in response to receiving loaded data for the replayed load instruction, testing for a data mis-speculation by comparing the loaded data for the replayed load instruction with the data loaded by the completed load instruction that is stored in the storage location.
    Type: Application
    Filed: October 31, 2019
    Publication date: October 8, 2020
    Applicant: Advanced Micro Devices, Inc.
    Inventors: John Kalamatianos, Susumu Mashimo, Krishnan V. Ramani, Scott Thomas Bingham
  • Publication number: 20200272463
    Abstract: A processor and method for handling lock instructions identifies which of a plurality of older store instructions relative to a current lock instruction are able to be locked. The method and processor lock the identified older store instructions as an atomic group with the current lock instruction. The method and processor negatively acknowledge probes until all of the older store instructions in the atomic group have written to cache memory. In some implementations, an atomic grouping unit issues an indication to lock identified older store instructions that are retired and lockable, and in some implementations, also issues an indication to lock older stores that are determined to be lockable that are non-retired.
    Type: Application
    Filed: February 27, 2019
    Publication date: August 27, 2020
    Inventors: Scott Thomas Bingham, Marius Evers, Krishnan V. Ramani, Thomas Kunjan
  • Publication number: 20190391808
    Abstract: A method and apparatus generates control information that indicates whether to change a counter value associated with a particular load instruction. In response to the control information, the method and apparatus causes a hysteresis effect for operating between a speculative mode and a non-speculative mode based on the counter value. The hysteresis effect is in favor of the non-speculative mode. The method and apparatus causes the hysteresis effect by incrementing the counter value associated with the particular load instruction by a first value or decrementing the counter value by a second value. The first value is greater than the second value.
    Type: Application
    Filed: June 20, 2018
    Publication date: December 26, 2019
    Inventors: Krishnan V. Ramani, Chetana N. Keltcher
  • Publication number: 20190310845
    Abstract: A system and method for tracking stores and loads to reduce load latency when forming the same memory address by bypassing a load store unit within an execution unit is disclosed. Store-load pairs which have a strong history of store-to-load forwarding are identified. Once identified, the load is memory renamed to the register stored by the store. The memory dependency predictor may also be used to detect loads that are dependent on a store but cannot be renamed. In such a configuration, the dependence is signaled to the load store unit and the load store unit uses the information to issue the load after the identified store has its physical address.
    Type: Application
    Filed: June 24, 2019
    Publication date: October 10, 2019
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Krishnan V. Ramani, Kai Troester, Frank C. Galloway, David N. Suggs, Michael D. Achenbach, Betty Ann McDaniel, Marius Evers
  • Patent number: 10331357
    Abstract: A system and method for tracking stores and loads to reduce load latency when forming the same memory address by bypassing a load store unit within an execution unit is disclosed. The system and method include storing data in one or more memory dependent architectural register numbers (MdArns), allocating the one or more MdArns to a MEMFILE, writing the allocated one or more MdArns to a map file, wherein the map file contains a MdArn map to enable subsequent access to an entry in the MEMFILE, upon receipt of a load request, checking a base, an index, a displacement and a match/hit via the map file to identify an entry in the MEMFILE and an associated store, and on a hit, providing the entry responsive to the load request from the one or more MdArns.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: June 25, 2019
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Betty Ann McDaniel, Michael D. Achenbach, David N. Suggs, Frank C. Galloway, Kai Troester, Krishnan V. Ramani
  • Patent number: 10241797
    Abstract: A method for reducing a number of operations replayed in a processor includes decoding an operation to determine a memory address and a command in the operation. If data is not in a way predictor based on the memory address, a suppress wakeup signal is sent to an operation scheduler, and the operation scheduler suppresses waking up other operations that are dependent on the data.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: March 26, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ganesh Venkataramanan, Mike Butler, Krishnan V. Ramani
  • Publication number: 20180052613
    Abstract: A system and method for tracking stores and loads to reduce load latency when forming the same memory address by bypassing a load store unit within an execution unit is disclosed. The system and method include storing data in one or more memory dependent architectural register numbers (MdArns), allocating the one or more MdArns to a MEMFILE, writing the allocated one or more MdArns to a map file, wherein the map file contains a MdArn map to enable subsequent access to an entry in the MEMFILE, upon receipt of a load request, checking a base, an index, a displacement and a match/hit via the map file to identify an entry in the MEMFILE and an associated store, and on a hit, providing the entry responsive to the load request from the one or more MdArns.
    Type: Application
    Filed: December 15, 2016
    Publication date: February 22, 2018
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Betty Ann McDaniel, Michael D. Achenbach, David N. Suggs, Frank C. Galloway, Kai Troester, Krishnan V. Ramani
  • Patent number: 8819397
    Abstract: Methods and apparatuses are provided for increased efficiency in a processor via control word prediction. The apparatus comprises an operational unit capable of determining whether an instruction will change a first control word to a second control word for processing dependent instructions. Execution units process the dependent instructions using a predicted control word and compare the second control word to the predicted control word. A scheduling unit causes the execution units to reprocess the dependent instructions when the predicted control word does not match the second control word. The method comprises determining that an instruction will change a first control word to a second control word and processing the dependent instructions using a predicted control word. The second control word is compared to the predicted control word and the dependent instructions are reprocessed using the second control word when the predicted control word does not match the second control word.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: August 26, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Michael D. Estlick, Jay Fleischman, Debjit Das Sarma, Emil Talpes, Krishnan V. Ramani, Chun Liu
  • Publication number: 20140025933
    Abstract: A method for reducing a number of operations replayed in a processor includes decoding an operation to determine a memory address and a command in the operation. If data is not in a way predictor based on the memory address, a suppress wakeup signal is sent to an operation scheduler, and the operation scheduler suppresses waking up other operations that are dependent on the data.
    Type: Application
    Filed: July 17, 2012
    Publication date: January 23, 2014
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Ganesh Venkataramanan, Mike Butler, Krishnan V. Ramani
  • Publication number: 20120226891
    Abstract: Methods and apparatuses are provided for increased efficiency in a processor via control word prediction. The apparatus comprises an operational unit capable of determining whether an instruction will change a first control word to a second control word for processing dependent instructions. Execution units process the dependent instructions using a predicted control word and compare the second control word to the predicted control word. A scheduling unit causes the execution units to reprocess the dependent instructions when the predicted control word does not match the second control word. The method comprises determining that an instruction will change a first control word to a second control word and processing the dependent instructions using a predicted control word. The second control word is compared to the predicted control word and the dependent instructions are reprocessed using the second control word when the predicted control word does not match the second control word.
    Type: Application
    Filed: March 1, 2011
    Publication date: September 6, 2012
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Michael D. ESTLICK, Jay FLEISCHMAN, Debjit Das Sarma, Emil TALPES, Krishnan V. RAMANI, Chun LIU
  • Patent number: 7263600
    Abstract: A system and method for linking speculative results of load operations to register values. A system includes a memory file including an entry configured to store a first addressing pattern and a first tag. The memory file is configured to compare the first addressing pattern to a second addressing pattern of a load operation, and to link a data value identified by the first tag to a speculative result of the load operation if there is a match. The system further includes an execution core coupled to the memory file and configured to access the speculative result when executing a second operation that is dependent on the load operation, and a load store unit coupled to the memory file and configured to verify the link between the data value and the speculative result of the load operation by performing a comparison between one or more addresses.
    Type: Grant
    Filed: May 5, 2004
    Date of Patent: August 28, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Benjamin T. Sander, Krishnan V. Ramani, Ramsey W. Haddad, Mitchell Alsup