Abstract: A decoding system for decoding a digital data stream that has been convolutionally encoded in accordance with a selected constraint length and selected polynomial codes, which system includes a processor, such as a Viterbi decoder, that is reconfigurable so that it can decode encoded digital data streams for a number of different user channels for which data streams have been convolutionally encoded in accordance with respectively different combinations of selected constraint length and selected polynomial codes.

Abstract: A video scrambling system scrambles adjacent sequentially odd and even video information lines of a video frame by simultaneously storing in a memory a pair of such adjacent lines; and forming a pair of scrambled video information lines by retrieving from the memory a segment of one of the stored video information lines followed by a segment of the other stored video information line, and by shifting the phase of one of the retrieved segments of the scrambled video information line in relation to the other retrieved segment of said scrambled video information line by an odd multiple of one-half the phase of the chrominance information cycle. This phase shift causes the phase relationship of all segments with respect to the color reference signal to be the same; and as a result there is no differential hue shift in the descrambled signal. In a complementary descrambling system, the two retrieved segments of each descrambled video information line are retrieved consecutively without an intervening phase shift.

Abstract: A decoding system capable of outputting Viterbi-decoding-algorithm-decoded data at a predetermined rate that is greater than a given rate at which coded data is processed in accordance with said algorithm to produce the decoded data. The system includes a data input bus; a data output bus; a ring of decoders, with each decoder being coupled to the input bus for receiving coded data from the input bus and coupled to the output bus for providing decoded data onto the output bus. Each of the decoders in the ring includes an input buffer, timing controller, decoding processor and output buffer. The input buffer responds to a start-input signal from a preceding decoder in the ring by buffering a block of the received coded data. The timing contoller provides a start-input signal to a succeeding decoder in the ring at such time as to cause the succeeding decoder to receive a block of coded data from the input bus that overlaps the block of coded data received from the input bus by the instant said decoder.