Patents by Inventor Krishnasawamy Nagaraj
Krishnasawamy Nagaraj has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240146323Abstract: Methods for operating two or more analog-to-digital converters (ADCs) are presented herein. The method may be implemented in an integrated circuit. The integrated circuit may include a first ADC and a second ADC disposed on a single semiconductor die. The integrated circuit may also include logic circuitry operably coupled to the first and second ADCs. For a digital value obtained by conversion, by the first ADC, of a first analog signal sampled by the first ADC during a period of time overlapping with another period of time during which a second analog signal is being converted by the second ADC, the logic circuitry may be configured to cause the digital value to be marked as noisy.Type: ApplicationFiled: October 28, 2022Publication date: May 2, 2024Inventors: Christy Leigh She, Joonsung Park, Krishnasawamy Nagaraj, Srinivasa Chakravarthy
-
Patent number: 11393971Abstract: An improved differential sensor and corresponding apparatus implementing same. The differential sensor includes a substrate, an amplifier coupled to the substrate, and a plurality of highly-matched piezoelectric capacitors formed onto the substrate. A first set of the highly-matched piezoelectric capacitors are electrically coupled to a non-inverting input of the amplifier, and a second set of the highly-matched piezoelectric capacitors are electrically coupled to an inverting input of the amplifier to form an open loop differential amplifier.Type: GrantFiled: November 27, 2018Date of Patent: July 19, 2022Assignee: Texas Instruments IncorporatedInventors: Sudhanshu Khanna, Michael Zwerg, Steven C. Bartling, Brian Elies, Krishnasawamy Nagaraj, Wei-Yan Shih
-
Publication number: 20210389174Abstract: In described examples, each node between adjacent capacitive elements of a stack of series-coupled capacitive elements is biased during a reset mode, where each of the capacitive elements includes piezoelectric material. A strain-induced voltage is generated across each of the capacitive elements. Each of the strain-induced voltages is combined to generate a piezoelectric-responsive output signal during a sensing mode at a time different from the time of the reset mode.Type: ApplicationFiled: August 31, 2021Publication date: December 16, 2021Inventors: Michael Zwerg, Sudhanshu Khanna, Steven C. Bartling, Brian Elies, Krishnasawamy Nagaraj, Wei-Yan Shih
-
Patent number: 11105676Abstract: In described examples, each node between adjacent capacitive elements of a stack of series-coupled capacitive elements is biased during a reset mode, where each of the capacitive elements includes piezoelectric material. A strain-induced voltage is generated across each of the capacitive elements. Each of the strain-induced voltages is combined to generate a piezoelectric-responsive output signal during a sensing mode at a time different from the time of the reset mode.Type: GrantFiled: November 14, 2018Date of Patent: August 31, 2021Assignee: Texas Instruments IncorporatedInventors: Michael Zwerg, Sudhanshu Khanna, Steven C. Bartling, Brian Elies, Krishnasawamy Nagaraj, Wei-Yan Shih
-
Publication number: 20200168786Abstract: An improved differential sensor and corresponding apparatus implementing same. The differential sensor includes a substrate, an amplifier coupled to the substrate, and a plurality of highly-matched piezoelectric capacitors formed onto the substrate. A first set of the highly-matched piezoelectric capacitors are electrically coupled to a non-inverting input of the amplifier, and a second set of the highly-matched piezoelectric capacitors are electrically coupled to an inverting input of the amplifier to form an open loop differential amplifier.Type: ApplicationFiled: November 27, 2018Publication date: May 28, 2020Inventors: Sudhanshu Khanna, Michael Zwerg, Steven C. Bartling, Brian Elies, Krishnasawamy Nagaraj, Wei-Yan Shih
-
Publication number: 20190369148Abstract: A capacitive sensing system includes a controller, a node connected to one side of a capacitance, the controller configured to measure the capacitance by measuring a time for a voltage across the capacitance to reach a predetermined reference voltage, a noise measurement circuit configured to measure electrical noise on the node, and the controller receiving the measurement of noise from the noise measurement circuit.Type: ApplicationFiled: August 14, 2019Publication date: December 5, 2019Inventors: Krishnasawamy Nagaraj, Paul Kimelman, Abhijit Kumar Das
-
Patent number: 10466286Abstract: A system includes a controller, a node connected to one side of a capacitance, the controller configured to measure the capacitance by measuring a time for a voltage across the capacitance to reach a predetermined reference voltage, and the controller causing the time period for capacitance measurements to vary even when the capacitance is constant.Type: GrantFiled: December 18, 2017Date of Patent: November 5, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Krishnasawamy Nagaraj, Paul Kimelman, Abhijit Kumar Das
-
Patent number: 10422822Abstract: A capacitive sensing system includes a controller, a node connected to one side of a capacitance, the controller configured to measure the capacitance by measuring a time for a voltage across the capacitance to reach a predetermined reference voltage, a noise measurement circuit configured to measure electrical noise on the node, and the controller receiving the measurement of noise from the noise measurement circuit.Type: GrantFiled: July 30, 2018Date of Patent: September 24, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Krishnasawamy Nagaraj, Paul Kimelman, Abhijit Kumar Das
-
Publication number: 20190162590Abstract: In described examples, each node between adjacent capacitive elements of a stack of series-coupled capacitive elements is biased during a reset mode, where each of the capacitive elements includes piezoelectric material. A strain-induced voltage is generated across each of the capacitive elements. Each of the strain-induced voltages is combined to generate a piezoelectric-responsive output signal during a sensing mode at a time different from the time of the reset mode.Type: ApplicationFiled: November 14, 2018Publication date: May 30, 2019Inventors: Michael Zwerg, Sudhanshu Khanna, Steven C. Bartling, Brian Elies, Krishnasawamy Nagaraj, Wei-Yan Shih
-
Publication number: 20180335459Abstract: A capacitive sensing system includes a controller, a node connected to one side of a capacitance, the controller configured to measure the capacitance by measuring a time for a voltage across the capacitance to reach a predetermined reference voltage, a noise measurement circuit configured to measure electrical noise on the node, and the controller receiving the measurement of noise from the noise measurement circuit.Type: ApplicationFiled: July 30, 2018Publication date: November 22, 2018Inventors: Krishnasawamy Nagaraj, Paul Kimelman, Abhijit Kumar Das
-
Patent number: 10060959Abstract: A capacitive sensing system includes a controller, a node connected to one side of a capacitance, the controller configured to measure the capacitance by measuring a time for a voltage across the capacitance to reach a predetermined reference voltage, a noise measurement circuit configured to measure electrical noise on the node, and the controller receiving the measurement of noise from the noise measurement circuit.Type: GrantFiled: February 25, 2014Date of Patent: August 28, 2018Assignee: Texas Instruments IncorporatedInventors: Krishnasawamy Nagaraj, Paul Kimelman, Abhijit Kumar Das
-
Publication number: 20180106844Abstract: A capacitive sensing system includes a controller, a node connected to one side of a capacitance, the controller configured to measure the capacitance by measuring a time for a voltage across the capacitance to reach a predetermined reference voltage, and the controller causing the time period for capacitance measurements to vary even when the capacitance is constant.Type: ApplicationFiled: December 18, 2017Publication date: April 19, 2018Inventors: Krishnasawamy Nagaraj, Paul Kimelman, Abhijit Kumar Das
-
Patent number: 9846185Abstract: A capacitive sensing system includes a controller, a node connected to one side of a capacitance, the controller configured to measure the capacitance by measuring a time for a voltage across the capacitance to reach a predetermined reference voltage, and the controller causing the time period for capacitance measurements to vary even when the capacitance is constant.Type: GrantFiled: February 25, 2014Date of Patent: December 19, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Krishnasawamy Nagaraj, Paul Kimelman, Abhijit Kumar Das
-
Patent number: 9742416Abstract: A phase detector includes a counter to generate the integer portion of a number of complete cycles of an output clock at each active edge of a reference clock. A time to digital converter in the phase detector generates the fractional portion of the number of complete cycles of the output clock at each active edge of the reference clock. The sum of the fractional portion and the integer portion is subtracted from an accumulated value obtained by accumulating a pre-determined number to generate an error signal as the output of the phase detector. The counter is read at an active edge of one of two re-timed clocks derived from the reference clock. Each of the two re-timed clocks is generated based on a comparison of the fractional portion with a pair of thresholds. Errors due to metastability in reading the counter are thereby avoided.Type: GrantFiled: February 15, 2012Date of Patent: August 22, 2017Assignee: Texas Instruments IncorporatedInventors: Indu Prathapan, Krishnasawamy Nagaraj, Frank Zhang
-
Patent number: 9520881Abstract: A system for tuning an oscillator frequency. The system includes a trimmed calibration circuit comprising a comparator and trimmed delay element and calibration logic. The calibration logic is configured to receive an output of the comparator and control an on time and an off time of an oscillator based on the output of the comparator.Type: GrantFiled: October 30, 2015Date of Patent: December 13, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Abhijit Kumar Das, Krishnasawamy Nagaraj, Rahul Bhandarkar
-
Publication number: 20140239977Abstract: A capacitive sensing system includes a controller, a node connected to one side of a capacitance, the controller configured to measure the capacitance by measuring a time for a voltage across the capacitance to reach a predetermined reference voltage, a noise measurement circuit configured to measure electrical noise on the node, and the controller receiving the measurement of noise from the noise measurement circuit.Type: ApplicationFiled: February 25, 2014Publication date: August 28, 2014Applicant: Texas Instruments IncorporatedInventors: Krishnasawamy Nagaraj, Paul Kimelman, Abhijit Kumar Das
-
Publication number: 20140239983Abstract: A capacitive sensing system includes a controller, a node connected to one side of a capacitance, the controller configured to measure the capacitance by measuring a time for a voltage across the capacitance to reach a predetermined reference voltage, and the controller causing the time period for capacitance measurements to vary even when the capacitance is constant.Type: ApplicationFiled: February 25, 2014Publication date: August 28, 2014Applicant: Texas Instruments IncorporatedInventors: Krishnasawamy Nagaraj, Paul Kimelman, Abhijit Kumar Das
-
Patent number: 8536910Abstract: A phased-locked loop (PLL) circuit which comprises a phase-frequency detector (PFD) configured to receive a reference signal, a voltage-controlled oscillator (VCO) configured to produce a VCO signal, and a divider configured to divide the VCO signal thereby producing a feedback signal based on the feedback signal not being locked to the reference signal. Based on the feedback signal not being locked to the reference signal, the PFD is configured to compare an edge of the reference signal with an edge of the feedback signal to produce an error signal. Based on the feedback signal being locked to the reference signal, the PFD is configured to compare the edge of the reference signal to an edge of the VCO signal to produce an error signal and the divider is configured to be disabled.Type: GrantFiled: June 20, 2011Date of Patent: September 17, 2013Assignee: Texas Instruments IncorporatedInventors: Krishnasawamy Nagaraj, Ajay Kumar
-
Publication number: 20130211758Abstract: A phase detector includes a counter to generate the integer portion of a number of complete cycles of an output clock at each active edge of a reference clock. A time to digital converter in the phase detector generates the fractional portion of the number of complete cycles of the output clock at each active edge of the reference clock. The sum of the fractional portion and the integer portion is subtracted from an accumulated value obtained by accumulating a pre-determined number to generate an error signal as the output of the phase detector. The counter is read at an active edge of one of two re-timed clocks derived from the reference clock. Each of the two re-timed clocks is generated based on a comparison of the fractional portion with a pair of thresholds. Errors due to metastability in reading the counter are thereby avoided.Type: ApplicationFiled: February 15, 2012Publication date: August 15, 2013Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Indu Prathapan, Krishnasawamy Nagaraj, Frank Zhang
-
Patent number: 8451159Abstract: A method for converting an analog signal to a digital signal is provided. Initially, a digital representation of a portion of an analog signal is generated. Residue of the analog signal is then sampled at a sampling instant so as to generate a residue sample. A signal having a frequency that is proportional to the voltage of the residue sample is generated, and the signal is measured to generate coarse and fine measurements of the frequency. A digital representation of the residue sample from the coarse and fine measurements is then generated.Type: GrantFiled: November 15, 2011Date of Patent: May 28, 2013Assignee: Texas Instruments IncorporatedInventors: Amit K. Gupta, Krishnasawamy Nagaraj