Patents by Inventor Krishnaswamy Ramkumar
Krishnaswamy Ramkumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11257912Abstract: A semiconductor device and method of manufacturing the same are provided. In one embodiment, method includes forming a first oxide layer over a substrate, forming a silicon-rich, oxygen-rich, oxynitride layer on the first oxide layer, forming a silicon-rich, nitrogen-rich, and oxygen-lean nitride layer over the oxynitride layer, and forming a second oxide layer on the nitride layer. Generally, the nitride layer includes a majority of charge traps distributed in the oxynitride layer and the nitride layer. Optionally, the method further includes forming a middle oxide layer between the oxynitride layer and the nitride layer. Other embodiments are also described.Type: GrantFiled: September 28, 2020Date of Patent: February 22, 2022Assignee: LONGITUDE FLASH MEMORY SOLUTIONS LTD.Inventors: Fredrick B. Jenne, Krishnaswamy Ramkumar
-
Patent number: 11222965Abstract: An embodiment of a semiconductor memory device including a multi-layer charge storing layer and methods of forming the same are described. Generally, the device includes a channel formed from a semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device; a tunnel oxide layer overlying the channel; and a multi-layer charge storing layer including an oxygen-rich, first oxynitride layer on the tunnel oxide layer in which a stoichiometric composition of the first oxynitride layer results in it being substantially trap free, and an oxygen-lean, second oxynitride layer on the first oxynitride layer in which a stoichiometric composition of the second oxynitride layer results in it being trap dense. In one embodiment, the device comprises a non-planar transistor including a gate having multiple surfaces abutting the channel, and the gate comprises the tunnel oxide layer and the multi-layer charge storing layer.Type: GrantFiled: December 24, 2019Date of Patent: January 11, 2022Assignee: LONGITUDE FLASH MEMORY SOLUTIONS LTDInventors: Sagy Charel Levy, Krishnaswamy Ramkumar, Fredrick Jenne, Sam G Geha
-
Publication number: 20220005929Abstract: Semiconductor devices including non-volatile memory transistors and methods of fabricating the same to improve performance thereof are provided. In one embodiment, the memory transistor comprises an oxide-nitride-oxide (ONO) stack on a surface of a semiconductor substrate, and a high work function gate electrode formed over a surface of the ONO stack. Preferably, the gate electrode comprises a doped polysilicon layer, and the ONO stack comprises multi-layer charge storing layer including at least a substantially trap free bottom oxynitride layer and a charge trapping top oxynitride layer. More preferably, the device also includes a metal oxide semiconductor (MOS) logic transistor formed on the same substrate, the logic transistor including a gate oxide and a high work function gate electrode. In certain embodiments, the dopant is a P+ dopant and the memory transistor comprises N-type (NMOS) silicon-oxide-nitride-oxide-silicon (SONOS) transistor while the logic transistor a P-type (PMOS) transistor.Type: ApplicationFiled: July 2, 2021Publication date: January 6, 2022Inventors: Igor Polishchuk, Sagy Charel Levy, Krishnaswamy Ramkumar
-
Publication number: 20210350850Abstract: A semiconductor inference device that has a non-volatile memory (NVM) array including NVM cells arranged in rows and columns, in which each NVM cell comprises a charge trapping transistor configured to store one of N×analog values corresponding to N×levels of its drain current (ID) or threshold voltage (VT) levels, representing N×weight values for multiply accumulate (MAC) operations. The semiconductor inference device also includes digital-to-analog (DAC) function and multiplexor (mux) function configured to generate an analog MAC result based on the digital inputs converted results and the weight values read results, and analog-to-digital (ADC) function configured to convert the analog MAC result of the mux function to a digital value. Other embodiments of the semiconductor inference device and related methods and systems are also disclosed.Type: ApplicationFiled: May 25, 2021Publication date: November 11, 2021Applicant: Cypress Semiconductor CorporationInventors: Venkataraman Prabhakar, Krishnaswamy Ramkumar, Vineet Agrawal, Long Hinh, Swatilekha Saha, Santanu Kumar Samanta, Michael Amundson, Ravindra M. Kapre
-
Publication number: 20210249254Abstract: A semiconductor device including an oxide-nitride-oxide (ONO) structure having a multi-layer charge storing layer and methods of forming the same are provided. Generally, the method involves: (i) forming a first oxide layer of the ONO structure; (ii) forming a multi-layer charge storing layer comprising nitride on a surface of the first oxide layer; and (iii) forming a second oxide layer of the ONO structure on a surface of the multi-layer charge storing layer. Preferably, the charge storing layer comprises at least two silicon oxynitride layers having differing stochiometric compositions of Oxygen, Nitrogen and/or Silicon. More preferably, the ONO structure is part of a silicon-oxide-nitride-oxide-silicon (SONOS) structure and the semiconductor device is a SONOS memory transistor. Other embodiments are also disclosed.Type: ApplicationFiled: January 25, 2021Publication date: August 12, 2021Inventors: Sagy Charel Levy, Krishnaswamy Ramkumar, Fredrick Jenne, Sam G. Geha
-
Publication number: 20210217862Abstract: An example memory device includes a channel positioned between and electrically connecting a first diffusion region and a second diffusion region, and a tunnel dielectric layer, a multi-layer charge trapping layer, and a blocking dielectric layer disposed between the gate structure and the channel. The multi-layer charge trapping layer includes a first dielectric layer disposed abutting a second dielectric layer and an anti-tunneling layer disposed between the first and second dielectric layers. The anti-tunneling layer includes an oxide layer. The first dielectric layer includes oxygen-rich nitride and the second dielectric layer includes oxygen-lean nitride.Type: ApplicationFiled: January 25, 2021Publication date: July 15, 2021Inventors: Igor Polishchuk, Sagy Charel Levy, Krishnaswamy Ramkumar
-
Patent number: 11056565Abstract: Semiconductor devices including non-volatile memory transistors and methods of fabricating the same to improve performance thereof are provided. In one embodiment, the memory transistor comprises an oxide-nitride-oxide (ONO) stack on a surface of a semiconductor substrate, and a high work function gate electrode formed over a surface of the ONO stack. Preferably, the gate electrode comprises a doped polysilicon layer, and the ONO stack comprises multi-layer charge storing layer including at least a substantially trap free bottom oxynitride layer and a charge trapping top oxynitride layer. More preferably, the device also includes a metal oxide semiconductor (MOS) logic transistor formed on the same substrate, the logic transistor including a gate oxide and a high work function gate electrode. In certain embodiments, the dopant is a P+ dopant and the memory transistor comprises N-type (NMOS) silicon-oxide-nitride-oxide-silicon (SONOS) transistor while the logic transistor a P-type (PMOS) transistor.Type: GrantFiled: October 14, 2019Date of Patent: July 6, 2021Assignee: LONGITUDE FLASH MEMORY SOLUTIONS LTD.Inventors: Igor Polishchuk, Sagy Charel Levy, Krishnaswamy Ramkumar
-
Publication number: 20210188629Abstract: An embodiment of a method of integration of a non-volatile memory device into a logic MOS flow is described. Generally, the method includes: forming a pad dielectric layer of a MOS device above a first region of a substrate; forming a channel of the memory device from a thin film of semiconducting material overlying a surface above a second region of the substrate, the channel connecting a source and drain of the memory device; forming a patterned dielectric stack overlying the channel above the second region, the patterned dielectric stack comprising a tunnel layer, a charge-trapping layer, and a sacrificial top layer; simultaneously removing the sacrificial top layer from the second region of the substrate, and the pad dielectric layer from the first region of the substrate; and simultaneously forming a gate dielectric layer above the first region of the substrate and a blocking dielectric layer above the charge-trapping layer.Type: ApplicationFiled: June 29, 2020Publication date: June 24, 2021Inventors: Krishnaswamy Ramkumar, Bo Jin, Fredrick B. Jenne
-
Publication number: 20210158868Abstract: A semiconductor device that has a semiconductor-oxide-nitride-oxide-semiconductor (SONOS) based non-volatile memory (NVM) array including NVM cells arranged in rows and columns, in which NVM transistors of the NVM cells are configured to store N×analog values corresponding to the N×levels of their drain current (ID) or threshold voltage (VT) levels, digital-to-analog (DAC) function that receives and converts digital signals from external devices, column multiplexor (mux) function that is configured to select and combine the analog value read from the NVM cells, and analog-to-digital (ADC) function that is configured to convert analog results of the column mux function to digital values and output the digital values.Type: ApplicationFiled: March 24, 2020Publication date: May 27, 2021Applicant: Cypress Semiconductor CorporationInventors: Venkataraman Prabhakar, Krishnaswamy Ramkumar, Vineet Argrawal, Long Hinh, Swatilekha Saha, Santanu Kumar Samanta, Michael Amundson, Ravindra Kapre
-
Publication number: 20210159346Abstract: A semiconductor device that has a silicon-oxide-nitride-oxide-silicon (SONOS) based non-volatile memory (NVM) array including charge-trapping memory cells arranged in rows and columns and configured to store one of N×analog values. Each charge-trapping memory cells may include a memory transistor including an angled lightly doped drain (LDD) implant extends at least partly under an oxide-nitride-oxide (ONO) layer of the memory transistor. The ONO layer disposed within the memory transistor and over an adjacent isolation structure has the same elevation substantially.Type: ApplicationFiled: March 24, 2020Publication date: May 27, 2021Applicant: Cypress Semiconductor CorporationInventors: Krishnaswamy Ramkumar, Venkatraman Prabhakar, Vineet Agrawal, Long Hinh, Santanu Kumar Samanta, Ravindra Kapre
-
Patent number: 11017851Abstract: A semiconductor device that has a semiconductor-oxide-nitride-oxide-semiconductor (SONOS) based non-volatile memory (NVM) array including NVM cells arranged in rows and columns, in which NVM transistors of the NVM cells are configured to store N×analog values corresponding to the N×levels of their drain current (ID) or threshold voltage (VT) levels, digital-to-analog (DAC) function that receives and converts digital signals from external devices, column multiplexor (mux) function that is configured to select and combine the analog value read from the NVM cells, and analog-to-digital (ADC) function that is configured to convert analog results of the column mux function to digital values and output the digital values.Type: GrantFiled: March 24, 2020Date of Patent: May 25, 2021Assignee: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Venkataraman Prabhakar, Krishnaswamy Ramkumar, Vineet Agrawal, Long Hinh, Swatilekha Saha, Santanu Kumar Samanta, Michael Amundson, Ravindra Kapre
-
Publication number: 20210104402Abstract: A method of scaling a nonvolatile trapped-charge memory device and the device made thereby is provided. In an embodiment, the method includes forming a channel region including polysilicon electrically connecting a source region and a drain region in a substrate. A tunneling layer is formed on the substrate over the channel region by oxidizing the substrate to form an oxide film and nitridizing the oxide film. A multi-layer charge trapping layer including an oxygen-rich first layer and an oxygen-lean second layer is formed on the tunneling layer, and a blocking layer deposited on the multi-layer charge trapping layer. In one embodiment, the method further includes a dilute wet oxidation to densify a deposited blocking oxide and to oxidize a portion of the oxygen-lean second layer.Type: ApplicationFiled: June 29, 2020Publication date: April 8, 2021Inventors: Fredrick B. Jenne, Sagy Charel Levy, Krishnaswamy Ramkumar
-
Publication number: 20210074822Abstract: A semiconductor device and method of manufacturing the same are provided. In one embodiment, method includes forming a first oxide layer over a substrate, forming a silicon-rich, oxygen-rich, oxynitride layer on the first oxide layer, forming a silicon-rich, nitrogen-rich, and oxygen-lean nitride layer over the oxynitride layer, and forming a second oxide layer on the nitride layer. Generally, the nitride layer includes a majority of charge traps distributed in the oxynitride layer and the nitride layer. Optionally, the method further includes forming a middle oxide layer between the oxynitride layer and the nitride layer. Other embodiments are also described.Type: ApplicationFiled: September 28, 2020Publication date: March 11, 2021Inventors: Fredrick B. Jenne, Krishnaswamy Ramkumar
-
Publication number: 20210074821Abstract: A method to integrate silicon-oxide-nitride-oxide-silicon (SONOS) transistors into a complementary metal-oxide-semiconductor (CMOS) flow including a triple gate oxide structure. The memory device may include a non-volatile memory (NVM) transistor that has a charge-trapping layer and a blocking dielectric, a first field-effect transistor (FET) including a first gate oxide of a first thickness, a second FET including a second gate oxide of a second thickness, a third FET including a third gate oxide of a third thickness, in which the first thickness is greater than the second thickness and the second thickness is greater than the third thickness.Type: ApplicationFiled: September 21, 2020Publication date: March 11, 2021Inventors: Krishnaswamy Ramkumar, Igor Kouznetsov, Venkatraman Prabhakar, Ali Keshavarzi
-
Patent number: 10903068Abstract: A semiconductor device including an oxide-nitride-oxide (ONO) structure having a multi-layer charge storing layer and methods of forming the same are provided. Generally, the method involves: (i) forming a first oxide layer of the ONO structure; (ii) forming a multi-layer charge storing layer comprising nitride on a surface of the first oxide layer; and (iii) forming a second oxide layer of the ONO structure on a surface of the multi-layer charge storing layer. Preferably, the charge storing layer comprises at least two silicon oxynitride layers having differing stochiometric compositions of Oxygen, Nitrogen and/or Silicon. More preferably, the ONO structure is part of a silicon-oxide-nitride-oxide-silicon (SONOS) structure and the semiconductor device is a SONOS memory transistor. Other embodiments are also disclosed.Type: GrantFiled: April 14, 2016Date of Patent: January 26, 2021Assignee: LONGITUDE FLASH MEMORY SOLUTIONS LTD.Inventors: Sagy Charel Levy, Krishnaswamy Ramkumar, Fredrick Jenne, Sam G. Geha
-
Patent number: 10903342Abstract: An embodiment of a semiconductor memory device including a multi-layer charge storing layer and methods of forming the same are described. Generally, the device includes a channel formed from a semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device; a tunnel oxide layer overlying the channel; and a multi-layer charge storing layer including an oxygen-rich, first oxynitride layer on the tunnel oxide layer in which a stoichiometric composition of the first oxynitride layer results in it being substantially trap free, and an oxygen-lean, second oxynitride layer on the first oxynitride layer in which a stoichiometric composition of the second oxynitride layer results in it being trap dense. In one embodiment, the device comprises a non-planar transistor including a gate having multiple surfaces abutting the channel, and the gate comprises the tunnel oxide layer and the multi-layer charge storing layer.Type: GrantFiled: May 30, 2018Date of Patent: January 26, 2021Assignee: LONGITUDE FLASH MEMORY SOLUTIONS LTD.Inventors: Sagy Levy, Krishnaswamy Ramkumar, Fredrick Jenne, Sam Geha
-
Patent number: 10896973Abstract: An embodiment of a semiconductor memory device including a multi-layer charge storing layer and methods of forming the same are described. Generally, the device includes a channel formed from a semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device; a tunnel oxide layer overlying the channel; and a multi-layer charge storing layer including an oxygen-rich, first oxynitride layer on the tunnel oxide layer in which a stoichiometric composition of the first oxynitride layer results in it being substantially trap free, and an oxygen-lean, second oxynitride layer on the first oxynitride layer in which a stoichiometric composition of the second oxynitride layer results in it being trap dense. In one embodiment, the device comprises a non-planar transistor including a gate having multiple surfaces abutting the channel, and the gate comprises the tunnel oxide layer and the multi-layer charge storing layer.Type: GrantFiled: May 30, 2018Date of Patent: January 19, 2021Assignee: LONGITUDE FLASH MEMORY SOLUTIONS LTD.Inventors: Sagy Levy, Krishnaswamy Ramkumar, Fredrick Jenne, Sam Geha
-
Patent number: 10854625Abstract: A method of fabricating a memory device is described. Generally, the method includes: forming on a surface of a substrate a dielectric stack including a tunneling dielectric and a charge-trapping layer overlying the tunneling dielectric; forming a cap layer overlying the dielectric stack, wherein the cap layer comprises a multi-layer cap layer including at least a first cap layer overlying the charge-trapping layer, and a second cap layer overlying the first cap layer; patterning the cap layer and the dielectric stack to form a gate stack of a memory device; removing the second cap layer; and performing an oxidation process to oxidize the first cap layer to form a blocking oxide overlying the charge-trapping layer, wherein the oxidation process consumes the first cap layer. Other embodiments are also described.Type: GrantFiled: September 23, 2019Date of Patent: December 1, 2020Assignee: Longitude Flash Memory Solutions Ltd.Inventor: Krishnaswamy Ramkumar
-
Publication number: 20200350213Abstract: Semiconductor devices and methods of manufacturing the same are provided. The semiconductor devices may have a memory array having two transistor (2T) memory cells, each including a non-volatile memory (NVM) transistor and a high voltage (HV) field-effect transistor (FET) as a select transistor. The devices further include a logic area in which HV FETs, input/output (I/) FETs, and low voltage (LV)/core FETs are formed thereon. Other embodiments are also described.Type: ApplicationFiled: June 16, 2020Publication date: November 5, 2020Inventors: Krishnaswamy Ramkumar, Venkatraman Prabhakar
-
Patent number: 10790364Abstract: A semiconductor device and method of manufacturing the same are provided. In one embodiment, method includes forming a first oxide layer over a substrate, forming a silicon-rich, oxygen-rich, oxynitride layer on the first oxide layer, forming a silicon-rich, nitrogen-rich, and oxygen-lean nitride layer over the oxynitride layer, and forming a second oxide layer on the nitride layer. Generally, the nitride layer includes a majority of charge traps distributed in the oxynitride layer and the nitride layer. Optionally, the method further includes forming a middle oxide layer between the oxynitride layer and the nitride layer. Other embodiments are also described.Type: GrantFiled: January 4, 2019Date of Patent: September 29, 2020Assignee: LONGITUDE FLASH MEMORY SOLUTIONS LTD.Inventors: Fredrick B. Jenne, Krishnaswamy Ramkumar