Abstract: A built-in self-test (BIST) system comprising repair logic structured to share state logic of failed memories across local registers located in a shared registry which services multiple memories, wherein each of the local registers is associated with a different memory.

Abstract: Aspects of the invention provide for reducing BIST test time for a memory of an IC chip. In one embodiment, a BIST architecture for reducing BIST test time of a memory for an integrated circuit (IC) chip, the architecture comprising: a pair of latches for receiving bursts of data from a memory; a first compression stage for receiving a burst of data and compressing the burst of data into a plurality of latches; a second compression stage for comparing the compressed bursts of data with expected data; and a logic gate for determining whether there is a fail in the burst of data.

Abstract: An integrated circuit chip with a built-in self-test (BIST) circuit having a BIST engine, which is electrically connected to multiple memories, which tests those multiple memories in parallel, and which incorporates an address generator. Prior to testing, the address generator generates a pair of tables. The tables include a first table, which indicates the highest decode numbers per specific bank numbers in all of the multiple memories, and a second table, which indicates the highest bank numbers per specific decode numbers in all of the multiple memories. During testing, the address generator sequentially and dynamically generates the specific test addresses to be swept and does so such that all of the specific test addresses are within a composite address space that is defined by one of the tables and by the highest maximum word line number in any of the memories. Also disclosed is an associated BIST method.

Abstract: Disclosed is a chip with a built-in self-test (BIST) circuit that incorporates a BIST engine that tests memories in parallel and that, prior to testing, dynamically sets the size of the address space to be swept. The BIST engine comprises an address generator that determines a superset of address space values associated with all the memories. This superset indicates the highest number of banks, the highest number of word lines per bank and the highest decode number for any of the memories. The address generator then generates test addresses and does so such that all test addresses are within a composite address space defined by the superset and, thereby within an address space that may, depending upon the memory configurations, be less than the predetermined maximum address space associated with such memories so as to reduce test time. Also disclosed is an associated BIST method for testing memories.

Abstract: Disclosed is an integrated circuit chip with a built-in self-test (BIST) circuit having a BIST engine, which is electrically connected to multiple memories, which tests those multiple memories in parallel, and which incorporates an address generator. Prior to testing, the address generator generates a pair of tables. The tables include a first table, which indicates the highest decode numbers per specific bank numbers in all of the multiple memories, and a second table, which indicates the highest bank numbers per specific decode numbers in all of the multiple memories. During testing, the address generator sequentially and dynamically generates the specific test addresses to be swept and does so such that all of the specific test addresses are within a composite address space that is defined by one of the tables and by the highest maximum word line number in any of the memories. Also disclosed is an associated BIST method.

Abstract: A BIST engine configured to store a per pattern based fail status during memory BIST run and related processes thereof are provided. The method includes testing a plurality of patterns in at least one memory device and determining which of the plurality of patterns has detected a fail during execution of each pattern. The method further includes storing a per pattern based fail status of each of the detected failed patterns.

Abstract: Disclosed is a chip with a built-in self-test (BIST) circuit that incorporates a BIST engine that tests memories in parallel and that, prior to testing, dynamically sets the size of the address space to be swept. The BIST engine comprises an address generator that determines a superset of address space values associated with all the memories. This superset indicates the highest number of banks, the highest number of word lines per bank and the highest decode number for any of the memories. The address generator then generates test addresses and does so such that all test addresses are within a composite address space defined by the superset and, thereby within an address space that may, depending upon the memory configurations, be less than the predetermined maximum address space associated with such memories so as to reduce test time. Also disclosed is an associated BIST method for testing memories.

Abstract: Aspects of the invention provide for decreasing the power supply demand during built-in self test (BIST) initializations. In one embodiment, a BIST architecture for reducing the power supply demand during BIST initializations, includes: a chain of slow BIST I/O interfaces; a chain of fast BIST I/O interfaces, each fast BIST I/O interface connected to a slow BIST I/O interface; and a BIST engine including a burst staggering latch for controlling a multiplexor within each of the slow BIST I/O interfaces, wherein the burst staggering latch, for a first burst signal, staggers the first burst signal to each of the slow BIST I/O interfaces, such that, during a first clock cycle, only a first slow BIST I/O interface receives the first burst signal.

Abstract: In a method of executing a BIST operation on IC memory arrays having a common BIST control unit, a first BIST sequence is initiated. Each address for the arrays is incremented. The BIST control unit receives a signal indicating a maximum valid address in the array is reached, receiving a plurality of maximum valid addresses, which are recorded. A single relatively highest maximum valid address is determined. A first mode, which prevents BIST testing, is engaged in each array having reached the maximum valid address. A second BIST sequence is initiated based on having received the signal indicating a maximum valid address is reached from all the arrays connected to the common BIST control unit. An address count is decremented from the single relatively highest maximum valid address. The first mode is disengaged for each array as the address count reaches each of the maximum valid addresses during the decrementing.

Abstract: Disclosed is a stacked chip module and associated method with integrated circuit (IC) chips having integratable built-in self-maintenance blocks. The module comprises a stack of chips and each chip comprises a self-maintenance block with first and second controllers. The first controller controls wafer-level and module-level servicing (e.g., self-testing or self-repairing) of an on-chip functional block. The second controller provides an interface between an off-chip tester and the first controller during wafer-level servicing. Each chip further comprises a plurality of interconnect structures (e.g., multiplexers and through-substrate-vias) that integrate the self-maintenance blocks of adjacent chips in the stack so that, during module-level servicing, a single second controller on a single one of the chips in the stack (e.g., the bottom chip) provides the only interface between the off-chip tester and all of the first controllers.

Abstract: Disclosed is a stacked chip module incorporating a stack of integrated circuit (IC) chips having integratable and automatically reconfigurable built-in self-maintenance blocks (i.e., built-in self-test (BIST) circuits or built-in self-repair (BISR) circuits). Integration of the built-in self-maintenance blocks between the IC chips in the stack allows for servicing (e.g., self-testing or self-repairing) of functional blocks at the module-level. Automatic reconfiguration of the built-in self-maintenance blocks further allows for functional blocks on any of the IC chips in the stack to be serviced at the module-level even when one or more controllers associated with a given built-in self-maintenance block on a given IC chip has been determined to be defective (e.g., during previous wafer-level servicing). Also disclosed is a method of manufacturing and servicing such a stacked chip module.

Abstract: Aspects of the invention provide for reducing BIST test time for a memory of an IC chip. In one embodiment, a BIST architecture for reducing BIST test time of a memory for an integrated circuit (IC) chip, the architecture comprising: a pair of latches for receiving bursts of data from a memory; a first compression stage for receiving a burst of data and compressing the burst of data into a plurality of latches; a second compression stage for comparing the compressed bursts of data with expected data; and a logic gate for determining whether there is a fail in the burst of data.

Abstract: Aspects of the invention provide for decreasing the power supply demand during built-in self test (BIST) initializations. In one embodiment, a BIST architecture for reducing the power supply demand during BIST initializations, includes: a chain of slow BIST I/O interfaces; a chain of fast BIST I/O interfaces, each fast BIST I/O interface connected to a slow BIST I/O interface; and a BIST engine including a burst staggering latch for controlling a multiplexor within each of the slow BIST I/O interfaces, wherein the burst staggering latch, for a first burst signal, staggers the first burst signal to each of the slow BIST I/O interfaces, such that, during a first clock cycle, only a first slow BIST I/O interface receives the first burst signal.

Abstract: In a method of executing a BIST operation on IC memory arrays having a common BIST control unit, a first BIST sequence is initiated. Each address for the arrays is incremented. The BIST control unit receives a signal indicating a maximum valid address in the array is reached, receiving a plurality of maximum valid addresses, which are recorded. A single relatively highest maximum valid address is determined. A first mode, which prevents BIST testing, is engaged in each array having reached the maximum valid address. A second BIST sequence is initiated based on having received the signal indicating a maximum valid address is reached from all the arrays connected to the common BIST control unit. An address count is decremented from the single relatively highest maximum valid address. The first mode is disengaged for each array as the address count reaches each of the maximum valid addresses during the decrementing.

Abstract: Disclosed is a stacked chip module incorporating a stack of integrated circuit (IC) chips having integratable and automatically reconfigurable built-in self-maintenance blocks (i.e., built-in self-test (BIST) circuits or built-in self-repair (BISR) circuits). Integration of the built-in self-maintenance blocks between the IC chips in the stack allows for servicing (e.g., self-testing or self-repairing) of functional blocks at the module-level. Automatic reconfiguration of the built-in self-maintenance blocks further allows for functional blocks on any of the IC chips in the stack to be serviced at the module-level even when one or more controllers associated with a given built-in self-maintenance block on a given IC chip has been determined to be defective (e.g., during previous wafer-level servicing). Also disclosed is a method of manufacturing and servicing such a stacked chip module.

Abstract: Disclosed is a stacked chip module and associated method with integrated circuit (IC) chips having integratable built-in self-maintenance blocks. The module comprises a stack of chips and each chip comprises a self-maintenance block with first and second controllers. The first controller controls wafer-level and module-level servicing (e.g., self-testing or self-repairing) of an on-chip functional block. The second controller provides an interface between an off-chip tester and the first controller during wafer-level servicing. Each chip further comprises a plurality of interconnect structures (e.g., multiplexers and through-substrate-vias) that integrate the self-maintenance blocks of adjacent chips in the stack so that, during module-level servicing, a single second controller on a single one of the chips in the stack (e.g., the bottom chip) provides the only interface between the off-chip tester and all of the first controllers.

Abstract: Self-test architectures are provided to implement data column and row redundancy with a totally integrated self-test and repair capability in a Random Access Memory (RAM), either a Dynamic RAM (DRAM) or a Static Ram (SRAM), and are particularly applicable to compileable memories and to embedded RAM within microprocessor or logic chips. The invention uses two passes of self-test of a memory. The first pass of self-test determines the worst failing column, the column with the largest number of unique failing row addresses. After completion of the first pass of self-test, the spare column is allocated to replace the worst failing column. In the second pass of self-test, the BIST (Built In Self-Test) collects unique failing row addresses as it does today for memories with spare rows only. At the completion of the second pass of self-test, the spare rows are then allocated.

Abstract: A structure and method for performing on-chip test runs and repairs of a memory chip. In the first test run and repair, a BIST circuit obtains the original combined repair solution from a fuse bay on the memory chip, runs the first test run for the memory chip, obtains a first test-run repair solution, and combines the original combined repair solution and the first test-run repair solution to obtain the latest/first combined repair solution. Then, an exclusive-OR gate is used to compare the first combined repair solution and the original combined repair solution to obtain a first new repair solution, which is programmed into the fuses of the fuse bay. As a result, the fuse bay stores the first combined repair solution. In the second test run and repair, a similar process is performed, and so on. As a result, any number of test runs and repairs can be performed on-chip for the memory chip.

Abstract: A structure and method for performing on-chip test runs and repairs of a memory chip. In the first test run and repair, a BIST circuit obtains the original combined repair solution from a fuse bay on the memory chip, runs the first test run for the memory chip, obtains a first test-run repair solution, and combines the original combined repair solution and the first test-run repair solution to obtain the latest/first combined repair solution. Then, an exclusive-OR gate is used to compare the first combined repair solution and the original combined repair solution to obtain a first new repair solution, which is programmed into the fuses of the fuse bay. As a result, the fuse bay stores the first combined repair solution. In the second test run and repair, a similar process is performed, and so on. As a result, any number of test runs and repairs can be performed on-chip for the memory chip.

Abstract: Self-test architectures are provided to implement data column and row redundancy with a totally integrated self-test and repair capability in a Random Access Memory (RAM), either a Dynamic RAM (DRAM) or a Static Ram (SRAM), and are particularly applicable to compileable memories and to embedded RAM within microprocessor or logic chips. The invention uses two passes of self-test of a memory. The first pass of self-test determines the worst failing column, the column with the largest number of unique failing row addresses. After completion of the first pass of self-test, the spare column is allocated to replace the worst failing column. In the second pass of self-test, the BIST (Built In Self-Test) collects unique failing row addresses as it does today for memories with spare rows only. At the completion of the second pass of self-test, the spare rows are then allocated.