Patents by Inventor Kristan D. Davis

Kristan D. Davis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Performing optimized collective operations in a irregular subcommunicator of compute nodes in a parallel computer
    Patent number: 10938889
    Abstract: In a parallel computer, performing optimized collective operations in an irregular subcommunicator of compute nodes may be carried out by: identifying, within the irregular subcommunicator, regular neighborhoods of compute nodes; selecting, for each neighborhood from the compute nodes of the neighborhood, a local root node; assigning each local root node to a node of a neighborhood-wide tree topology; mapping, for each neighborhood, the compute nodes of the neighborhood to a local tree topology having, at its root, the local root node of the neighborhood; and performing a one way, rooted collective operation within the subcommunicator including: performing, in one phase, the collective operation within each neighborhood; and performing, in another phase, the collective operation amongst the local root nodes.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: March 2, 2021
    Assignee: International Business Machines Corporation
    Inventors: Kristan D. Davis, Daniel A. Faraj
  • PERFORMING OPTIMIZED COLLECTIVE OPERATIONS IN AN IRREGULAR SUBCOMMUNICATOR OF COMPUTE NODES IN A PARALLEL COMPUTER
    Publication number: 20200028891
    Abstract: In a parallel computer, performing optimized collective operations in an irregular subcommunicator of compute nodes may be carried out by: identifying, within the irregular subcommunicator, regular neighborhoods of compute nodes; selecting, for each neighborhood from the compute nodes of the neighborhood, a local root node; assigning each local root node to a node of a neighborhood-wide tree topology; mapping, for each neighborhood, the compute nodes of the neighborhood to a local tree topology having, at its root, the local root node of the neighborhood; and performing a one way, rooted collective operation within the subcommunicator including: performing, in one phase, the collective operation within each neighborhood; and performing, in another phase, the collective operation amongst the local root nodes.
    Type: Application
    Filed: June 11, 2019
    Publication date: January 23, 2020
    Inventors: KRISTAN D. DAVIS, DANIEL A. FARAJ
  • Performing optimized collective operations in an irregular subcommunicator of compute nodes in a parallel computer
    Patent number: 10382527
    Abstract: In a parallel computer, performing optimized collective operations in an irregular subcommunicator of compute nodes may be carried out by: identifying, within the irregular subcommunicator, regular neighborhoods of compute nodes; selecting, for each neighborhood from the compute nodes of the neighborhood, a local root node; assigning each local root node to a node of a neighborhood-wide tree topology; mapping, for each neighborhood, the compute nodes of the neighborhood to a local tree topology having, at its root, the local root node of the neighborhood; and performing a one way, rooted collective operation within the subcommunicator including: performing, in one phase, the collective operation within each neighborhood; and performing, in another phase, the collective operation amongst the local root nodes.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: August 13, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kristan D. Davis, Daniel A. Faraj
  • Event and alert analysis in a distributed processing system
    Patent number: 10171289
    Abstract: Methods, apparatuses, and computer program products for event and alert analysis are provided. Embodiments include a local event analyzer embedded in an alert analyzer receiving events from an event queue. Embodiments also include the local event analyzer creating, based on the received events and local event analysis rules specific to the alert analyzer, a temporary alert for the alert analyzer. Embodiments also include the alert analyzer analyzing the temporary alert based on alert analysis rules.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Lynn A. Boger, James E. Carey, Kristan D. Davis, Philip J. Sanders
  • Multi-petascale highly efficient parallel supercomputer
    Patent number: 9971713
    Abstract: A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaflop-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC). The ASIC nodes are interconnected by a five dimensional torus network that optimally maximize the throughput of packet communications between nodes and minimize latency. The network implements collective network and a global asynchronous network that provides global barrier and notification functions. Integrated in the node design include a list-based prefetcher. The memory system implements transaction memory, thread level speculation, and multiversioning cache that improves soft error rate at the same time and supports DMA functionality allowing for parallel processing message-passing.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: May 15, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sameh Asaad, Ralph E. Bellofatto, Michael A. Blocksome, Matthias A. Blumrich, Peter Boyle, Jose R. Brunheroto, Dong Chen, Chen-Yong Cher, George L. Chiu, Norman Christ, Paul W. Coteus, Kristan D. Davis, Gabor J. Dozsa, Alexandre E. Eichenberger, Noel A. Eisley, Matthew R. Ellavsky, Kahn C. Evans, Bruce M. Fleischer, Thomas W. Fox, Alan Gara, Mark E. Giampapa, Thomas M. Gooding, Michael K. Gschwind, John A. Gunnels, Shawn A. Hall, Rudolf A. Haring, Philip Heidelberger, Todd A. Inglett, Brant L. Knudson, Gerard V. Kopcsay, Sameer Kumar, Amith R. Mamidala, James A. Marcella, Mark G. Megerian, Douglas R. Miller, Samuel J. Miller, Adam J. Muff, Michael B. Mundy, John K. O'Brien, Kathryn M. O'Brien, Martin Ohmacht, Jeffrey J. Parker, Ruth J. Poole, Joseph D. Ratterman, Valentina Salapura, David L. Satterfield, Robert M. Senger, Burkhard Steinmacher-Burow, William M. Stockdell, Craig B. Stunkel, Krishnan Sugavanam, Yutaka Sugawara, Todd E. Takken, Barry M. Trager, James L. Van Oosten, Charles D. Wait, Robert E. Walkup, Alfred T. Watson, Robert W. Wisniewski, Peng Wu
  • Event and alert analysis in a distributed processing system
    Patent number: 9602337
    Abstract: Methods, apparatuses, and computer program products for event and alert analysis are provided. Embodiments include a local event analyzer embedded in an alert analyzer receiving events from an event queue. Embodiments also include the local event analyzer creating, based on the received events and local event analysis rules specific to the alert analyzer, a temporary alert for the alert analyzer. Embodiments also include the alert analyzer analyzing the temporary alert based on alert analysis rules.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: March 21, 2017
    Assignee: International Business Machines Corporation
    Inventors: Lynn A. Boger, James E. Carey, Kristan D. Davis, Philip J. Sanders
  • EVENT AND ALERT ANALYSIS IN A DISTRIBUTED PROCESSING SYSTEM
    Publication number: 20160204975
    Abstract: Methods, apparatuses, and computer program products for event and alert analysis are provided. Embodiments include a local event analyzer embedded in an alert analyzer receiving events from an event queue. Embodiments also include the local event analyzer creating, based on the received events and local event analysis rules specific to the alert analyzer, a temporary alert for the alert analyzer. Embodiments also include the alert analyzer analyzing the temporary alert based on alert analysis rules.
    Type: Application
    Filed: February 22, 2016
    Publication date: July 14, 2016
    Inventors: LYNN A. BOGER, JAMES E. CAREY, KRISTAN D. DAVIS, PHILIP J. SANDERS
  • Identifying a largest logical plane from a plurality of logical planes formed of compute nodes of a subcommunicator in a parallel computer
    Patent number: 9390054
    Abstract: In a parallel computer, a largest logical plane from a plurality of logical planes formed of compute nodes of a subcommunicator may be identified by: identifying, by each compute node of the subcommunicator, all logical planes that include the compute node; calculating, by each compute node for each identified logical plane that includes the compute node, an area of the identified logical plane; initiating, by a root node of the subcommunicator, a gather operation; receiving, by the root node from each compute node of the subcommunicator, each node's calculated areas as contribution data to the gather operation; and identifying, by the root node in dependence upon the received calculated areas, a logical plane of the subcommunicator having the greatest area.
    Type: Grant
    Filed: October 14, 2013
    Date of Patent: July 12, 2016
    Assignee: International Business Machines Corporation
    Inventors: Kristan D. Davis, Daniel A. Faraj
  • Identifying logical planes formed of compute nodes of a subcommunicator in a parallel computer
    Patent number: 9330059
    Abstract: In a parallel computer, a plurality of logical planes formed of compute nodes of a subcommunicator may be identified by: for each compute node of the subcommunicator and for a number of dimensions beginning with a first dimension: establishing, by a plane building node, in a positive direction of the first dimension, all logical planes that include the plane building node and compute nodes of the subcommunicator in a positive direction of a second dimension, where the second dimension is orthogonal to the first dimension; and establishing, by the plane building node, in a negative direction of the first dimension, all logical planes that include the plane building node and compute nodes of the subcommunicator in the positive direction of the second dimension.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: May 3, 2016
    Assignee: International Business Machines Corporation
    Inventors: Kristan D. Davis, Daniel A. Faraj
  • Identifying logical planes formed of compute nodes of a subcommunicator in a parallel computer
    Patent number: 9275007
    Abstract: In a parallel computer, a plurality of logical planes formed of compute nodes of a subcommunicator may be identified by: for each compute node of the subcommunicator and for a number of dimensions beginning with a first dimension: establishing, by a plane building node, in a positive direction of the first dimension, all logical planes that include the plane building node and compute nodes of the subcommunicator in a positive direction of a second dimension, where the second dimension is orthogonal to the first dimension; and establishing, by the plane building node, in a negative direction of the first dimension, all logical planes that include the plane building node and compute nodes of the subcommunicator in the positive direction of the second dimension.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: March 1, 2016
    Assignee: International Business Machines Corporation
    Inventors: Kristan D. Davis, Daniel A. Faraj
  • Determining whether to send an alert in a distributed processing system
    Patent number: 9256482
    Abstract: Methods, apparatuses, and computer program products for determining whether to send an alert are provided. Embodiments include a voting manager receiving from a plurality of alert analyzers, one or more delivery codes associated with an alert. In dependence upon the one or more delivery codes, the voting manager determines whether to suppress the alert, to close the alert, or to report the alert.
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: February 9, 2016
    Assignee: International Business Machines Corporation
    Inventors: Lynn A. Boger, James E. Carey, Kristan D. Davis, Philip J. Sanders
  • MULTI-PETASCALE HIGHLY EFFICIENT PARALLEL SUPERCOMPUTER
    Publication number: 20160011996
    Abstract: A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaflop-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC). The ASIC nodes are interconnected by a five dimensional torus network that optimally maximize the throughput of packet communications between nodes and minimize latency. The network implements collective network and a global asynchronous network that provides global barrier and notification functions. Integrated in the node design include a list-based prefetcher. The memory system implements transaction memory, thread level speculation, and multiversioning cache that improves soft error rate at the same time and supports DMA functionality allowing for parallel processing message-passing.
    Type: Application
    Filed: April 30, 2015
    Publication date: January 14, 2016
    Inventors: Sameh Asaad, Ralph E. Bellofatto, Michael A. Blocksome, Matthias A. Blumrich, Peter Boyle, Jose R. Brunheroto, Dong Chen, Chen-Yong Cher, George L. Chiu, Norman Christ, Paul W. Coteus, Kristan D. Davis, Gabor J. Dozsa, Alexandre E. Eichenberger, Noel A. Eisley, Matthew R. Ellavsky, Kahn C. Evans, Bruce M. Fleischer, Thomas W. Fox, Alan Gara, Mark E. Giampapa, Thomas M. Gooding, Michael K. Gschwind, John A. Gunnels, Shawn A. Hall, Rudolf A. Haring, Philip Heidelberger, Todd A. Inglett, Brant L. Knudson, Gerard V. Kopcsay, Sameer Kumar, Amith R. Mamidala, James A. Marcella, Mark G. Megerian, Douglas R. Miller, Samuel J. Miller, Adam J. Muff, Michael B. Mundy, John K. O'Brien, Kathryn M. O'Brien, Martin Ohmacht, Jeffrey J. Parker, Ruth J. Poole, Joseph D. Ratterman, Valentina Salapura, David L. Satterfield, Robert M. Senger, Burkhard Steinmacher-Burow, William M. Stockdell, Craig B. Stunkel, Krishnan Sugavanam, Yutaka Sugawara, Todd E. Takken, Barry M. Trager, James L. Van Oosten, Charles D. Wait, Robert E. Walkup, Alfred T. Watson, Robert W. Wisniewski, Peng Wu
  • Servicing a globally broadcast interrupt signal in a multi-threaded computer
    Patent number: 9223729
    Abstract: Methods, apparatuses, and computer program products for servicing a globally broadcast interrupt signal in a multi-threaded computer comprising a plurality of processor threads. Embodiments include an interrupt controller indicating in a plurality of local interrupt status locations that a globally broadcast interrupt signal has been received by the interrupt controller. Embodiments also include a thread determining that a local interrupt status location corresponding to the thread indicates that the globally broadcast interrupt signal has been received by the interrupt controller. Embodiments also include the thread processing one or more entries in a global interrupt status bit queue based on whether global interrupt status bits associated with the globally broadcast interrupt signal are locked. Each entry in the global interrupt status bit queue corresponds to a queued global interrupt.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: December 29, 2015
    Assignee: International Business Machines Corporation
    Inventors: John E. Attinella, Kristan D. Davis, Roy G. Musselman, David L. Satterfield
  • Servicing a globally broadcast interrupt signal in a multi-threaded computer
    Patent number: 9223728
    Abstract: Methods, apparatuses, and computer program products for servicing a globally broadcast interrupt signal in a multi-threaded computer comprising a plurality of processor threads. Embodiments include an interrupt controller indicating in a plurality of local interrupt status locations that a globally broadcast interrupt signal has been received by the interrupt controller. Embodiments also include a thread determining that a local interrupt status location corresponding to the thread indicates that the globally broadcast interrupt signal has been received by the interrupt controller. Embodiments also include the thread processing one or more entries in a global interrupt status bit queue based on whether global interrupt status bits associated with the globally broadcast interrupt signal are locked. Each entry in the global interrupt status bit queue corresponds to a queued global interrupt.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: December 29, 2015
    Assignee: International Business Machines Corporation
    Inventors: John E. Attinella, Kristan D. Davis, Roy G. Musselman, David L. Satterfield
  • Checkpointing for delayed alert creation
    Patent number: 9086968
    Abstract: Methods, apparatuses, and computer program products for checkpointing for delayed alert creation are provided. Embodiments include applying a checkpoint to an events pool having events with corresponding alerts that have been generated and not delivered and following a crash and loss of the corresponding alerts not recorded in an alert database, generating new alerts based on the events in the events pool having the checkpoint. In response to completing processing of a new alert, embodiments include determining whether the alert database has an entry corresponding to the processed new alert. If the alert database has an entry corresponding to the processed new alert, embodiments include delivering the processed new alert without reporting the processed new alert to the alert database. If the alert database does not have an entry corresponding to the processed new alert, embodiments include reporting the processed new alert to an alert database.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: July 21, 2015
    Assignee: International Business Machines Corporation
    Inventors: Lynn A. Boger, James E. Carey, Kristan D. Davis, Philip J. Sanders
  • Multi-petascale highly efficient parallel supercomputer
    Patent number: 9081501
    Abstract: A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC).
    Type: Grant
    Filed: January 10, 2011
    Date of Patent: July 14, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sameh Asaad, Ralph E. Bellofatto, Michael A. Blocksome, Matthias A. Blumrich, Peter Boyle, Jose R. Brunheroto, Dong Chen, Chen-Yong Cher, George L. Chiu, Norman Christ, Paul W. Coteus, Kristan D. Davis, Gabor J. Dozsa, Alexandre E. Eichenberger, Noel A. Eisley, Matthew R. Ellavsky, Kahn C. Evans, Bruce M. Fleischer, Thomas W. Fox, Alan Gara, Mark E. Giampapa, Thomas M. Gooding, Michael K. Gschwind, John A. Gunnels, Shawn A. Hall, Rudolf A. Haring, Philip Heidelberger, Todd A. Inglett, Brant L. Knudson, Gerard V. Kopcsay, Sameer Kumar, Amith R. Mamidala, James A. Marcella, Mark G. Megerian, Douglas R. Miller, Samuel J. Miller, Adam J. Muff, Michael B. Mundy, John K. O'Brien, Kathryn M. O'Brien, Martin Ohmacht, Jeffrey J. Parker, Ruth J. Poole, Joseph D. Ratterman, Valentina Salapura, David L. Satterfield, Robert M. Senger, Brian Smith, Burkhard Steinmacher-Burow, William M. Stockdell, Craig B. Stunkel, Krishnan Sugavanam, Yutaka Sugawara, Todd E. Takken, Barry M. Trager, James L. Van Oosten, Charles D. Wait, Robert E. Walkup, Alfred T. Watson, Robert W. Wisniewski, Peng Wu
  • Identifying A Largest Logical Plane From A Plurality Of Logical Planes Formed Of Compute Nodes Of A Subcommunicator In A Parallel Computer
    Publication number: 20150106482
    Abstract: In a parallel computer, a largest logical plane from a plurality of logical planes formed of compute nodes of a subcommunicator may be identified by: identifying, by each compute node of the subcommunicator, all logical planes that include the compute node; calculating, by each compute node for each identified logical plane that includes the compute node, an area of the identified logical plane; initiating, by a root node of the subcommunicator, a gather operation; receiving, by the root node from each compute node of the subcommunicator, each node's calculated areas as contribution data to the gather operation; and identifying, by the root node in dependence upon the received calculated areas, a logical plane of the subcommunicator having the greatest area.
    Type: Application
    Filed: October 14, 2013
    Publication date: April 16, 2015
    Applicant: International Business Machines Corporation
    Inventors: KRISTAN D. DAVIS, DANIEL A. FARAJ
  • PERFORMING OPTIMIZED COLLECTIVE OPERATIONS IN AN IRREGULAR SUBCOMMUNICATOR OF COMPUTE NODES IN A PARALLEL COMPUTER
    Publication number: 20150106419
    Abstract: In a parallel computer, performing optimized collective operations in an irregular subcommunicator of compute nodes may be carried out by: identifying, within the irregular subcommunicator, regular neighborhoods of compute nodes; selecting, for each neighborhood from the compute nodes of the neighborhood, a local root node; assigning each local root node to a node of a neighborhood-wide tree topology; mapping, for each neighborhood, the compute nodes of the neighborhood to a local tree topology having, at its root, the local root node of the neighborhood; and performing a one way, rooted collective operation within the subcommunicator including: performing, in one phase, the collective operation within each neighborhood; and performing, in another phase, the collective operation amongst the local root nodes.
    Type: Application
    Filed: October 16, 2013
    Publication date: April 16, 2015
    Applicant: International Business Machines Corporation
    Inventors: Kristan D. Davis, Daniel A. Faraj
  • EVENT AND ALERT ANALYSIS IN A DISTRIBUTED PROCESSING SYSTEM
    Publication number: 20150074164
    Abstract: Methods, apparatuses, and computer program products for event and alert analysis are provided. Embodiments include a local event analyzer embedded in an alert analyzer receiving events from an event queue. Embodiments also include the local event analyzer creating, based on the received events and local event analysis rules specific to the alert analyzer, a temporary alert for the alert analyzer. Embodiments also include the alert analyzer analyzing the temporary alert based on alert analysis rules.
    Type: Application
    Filed: September 11, 2013
    Publication date: March 12, 2015
    Applicant: International Business Machines Corporation
    Inventors: LYNN A. BOGER, JAMES E. CAREY, KRISTAN D. DAVIS, PHILIP J. SANDERS
  • Checkpointing For Delayed Alert Creation
    Publication number: 20150074472
    Abstract: Methods, apparatuses, and computer program products for checkpointing for delayed alert creation are provided. Embodiments include applying a checkpoint to an events pool having events with corresponding alerts that have been generated and not delivered and following a crash and loss of the corresponding alerts not recorded in an alert database, generating new alerts based on the events in the events pool having the checkpoint. In response to completing processing of a new alert, embodiments include determining whether the alert database has an entry corresponding to the processed new alert. If the alert database has an entry corresponding to the processed new alert, embodiments include delivering the processed new alert without reporting the processed new alert to the alert database. If the alert database does not have an entry corresponding to the processed new alert, embodiments include reporting the processed new alert to an alert database.
    Type: Application
    Filed: September 11, 2013
    Publication date: March 12, 2015
    Applicant: International Business Machines Corporation
    Inventors: Lynn A. Boger, James E. Carey, Kristan D. Davis, Philip J. Sanders