Patents by Inventor Kristan J. Monsen

Kristan J. Monsen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8640129
    Abstract: According to some embodiments, a multithreaded microcontroller includes a thread control unit comprising thread control hardware (logic) configured to perform a number of multithreading system calls essentially in real time, e.g. in one or a few clock cycles. System calls can include mutex lock, wait condition, and signal instructions. The thread controller includes a number of thread state, mutex, and condition variable registers used for executing the multithreading system calls. Threads can transition between several states including free, run, ready and wait. The wait state includes interrupt, condition, mutex, I-cache, and memory substrates. A thread state transition controller controls thread states, while a thread instructions execution unit executes multithreading system calls and manages thread priorities to avoid priority inversion. A thread scheduler schedules threads according to their priorities.
    Type: Grant
    Filed: June 17, 2010
    Date of Patent: January 28, 2014
    Assignee: Geo Semiconductor Inc.
    Inventors: Sorin C. Cismas, Ilie Garbacea, Kristan J. Monsen
  • Publication number: 20100257534
    Abstract: According to some embodiments, a multithreaded microcontroller includes a thread control unit comprising thread control hardware (logic) configured to perform a number of multithreading system calls essentially in real time, e.g. in one or a few clock cycles. System calls can include mutex lock, wait condition, and signal instructions. The thread controller includes a number of thread state, mutex, and condition variable registers used for executing the multithreading system calls. Threads can transition between several states including free, run, ready and wait. The wait state includes interrupt, condition, mutex, I-cache, and memory substrates. A thread state transition controller controls thread states, while a thread instructions execution unit executes multithreading system calls and manages thread priorities to avoid priority inversion. A thread scheduler schedules threads according to their priorities.
    Type: Application
    Filed: June 17, 2010
    Publication date: October 7, 2010
    Inventors: Sorin C. Cismas, Ilie Garbacea, Kristan J. Monsen
  • Patent number: 7765547
    Abstract: According to some embodiments, a multithreaded microcontroller includes a thread control unit comprising thread control hardware (logic) configured to perform a number of multithreading system calls essentially in real time, e.g. in one or a few clock cycles. System calls can include mutex lock, wait condition, and signal instructions. The thread controller includes a number of thread state, mutex, and condition variable registers used for executing the multithreading system calls. Threads can transition between several states including free, run, ready and wait. The wait state includes interrupt, condition, mutex, I-cache, and memory substates. A thread state transition controller controls thread states, while a thread instructions execution unit executes multithreading system calls and manages thread priorities to avoid priority inversion. A thread scheduler schedules threads according to their priorities.
    Type: Grant
    Filed: November 24, 2004
    Date of Patent: July 27, 2010
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Sorin C. Cismas, Ilie Garbacea, Kristan J. Monsen
  • Patent number: 6996799
    Abstract: An integrated circuit is designed by interconnecting pre-designed data-driven cores (intellectual property, functional blocks). Hardware description language (e.g. Verilog or VHDL) and software language (e.g. C or C++) code for interconnecting the cores is automatically generated by software tools from a central circuit specification. The central specification recites pre-designed hardware cores (intellectual property) and the interconnections between the cores. HDL and software language test benches, and timing constraints are also automatically generated from the central specification. The automatic generation of code simplifies the interconnection of pre-existing cores for the design of complex integrated circuits.
    Type: Grant
    Filed: August 8, 2000
    Date of Patent: February 7, 2006
    Assignee: Mobilygen Corporation
    Inventors: Sorin C. Cismas, Kristan J. Monsen, Henry K. So