Abstract: This disclosure describes a multi-height routing cell and utilization of the multi-height routing in an integrated circuit to reduce routing congestion in a standard cell design floorplan. The multi-height routing cell includes a bypass connection, or “tunnel,” that routes a signal through a non-routing layer and under an impeding power rail. The multi-height routing cell includes bypass connectors on both sides of the bypass connection that provide connection points for which to connect standard cells on opposite sides of the impeding power rail. As such, the multi-height routing cell provides a route underneath the impeding power rail and, in turn, reducing routing congestion in the standard cell design floorplan.

Abstract: This disclosure describes a multi-height routing cell and utilization of the multi-height routing in an integrated circuit to reduce routing congestion in a standard cell design floorplan. The multi-height routing cell includes a bypass connection, or “tunnel,” that routes a signal through a non-routing layer and under an impeding power rail. The multi-height routing cell includes bypass connectors on both sides of the bypass connection that provide connection points for which to connect standard cells on opposite sides of the impeding power rail. As such, the multi-height routing cell provides a route underneath the impeding power rail and, in turn, reducing routing congestion in the standard cell design floorplan.

Abstract: This disclosure describes a multi-height routing cell and utilization of the multi-height routing in an integrated circuit to reduce routing congestion in a standard cell design floorplan. The multi-height routing cell includes a bypass connection, or “tunnel,” that routes a signal through a non-routing layer and under an impeding power rail. The multi-height routing cell includes bypass connectors on both sides of the bypass connection that provide connection points for which to connect standard cells on opposite sides of the impeding power rail. As such, the multi-height routing cell provides a route underneath the impeding power rail and, in turn, reducing routing congestion in the standard cell design floorplan.

Abstract: An execution unit (2) interface protocol allowing flow-through of data, where a function is specified once and the execution unit performs the function for multiple sets of input data. Function execution is pipelined through the execution unit, where an input unit (6) stores information, while a function logic unit (4) processes data and an output unit (8) holds results to be output. The execution unit (2) allows for data rate distortion, in applications such as data compression, where the amount of data received is different from the amount of data generated as output.

Abstract: A programmable clock generator (220), which is part of an integrated circuit (IC) (210), provides clock signals (230) and (232) to various components of the IC. The clock generator includes a PLL (322) and one or more choppers (326, 328) which provide a desired waveform to the IC for testing purposes. When used in conjunction with a tester (212, 312), the IC can be scan tested at-speed using slower and less expensive testing equipment.

Abstract: Direct memory access controller (DMAC) (54) adapted to directly execute C language style FOR tasks assigned by a processor (70), where the FOR task includes a movement of a data element from a first location to a second location in memory. The DMAC includes multiple execution units (EUs) (88, 90, 92), each to perform an arithmetic or logical operation, and a FOR task controller (80, 82, 86) to perform the data movement. The FOR task controller selects the operation to be performed by the EU. In one embodiment, the FOR task is made up of C language type FOR loops, where descriptors identify the control and body of the loop. The descriptors identify the source of operands for an EU, and the source may be changed within a FOR task. A descriptor specifies a function code for an EU and may specify multiple sets of operands for the EU.

Abstract: Direct memory access controller (DMA) (2) adapted to directly execute C language style FOR tasks, where the FOR task includes a movement of a data element from a first location to a second location in memory, and the movement is controlled by a master DMA engine (MDE) (6). A master DMA engine (MDE) (6) includes a top level state machine (52) to coordinate a context save state machine (54), a parse state machine (56), and a running state machine (58). An loop control descriptor (LCD) queue (74) and a data routing descriptor (DRD) cache store information. The LCD queue allows pipelining of descriptor parsing, while the DRD cache avoids refetching of DRDs on reentry of loops.