Patents by Inventor Kristen M. Tucker

Kristen M. Tucker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Efficient utilization of a multi-source network of control logic to achieve timing closure in a clocked logic circuit
    Patent number: 7979732
    Abstract: A method, system, and computer program product are provided for achieving timing closure in a clocked logic circuit. For each local clock buffer in a set of local clock buffers, a logic synthesis tool determines a clock control signal input from a set of clock control signal inputs that will drive a clock control signal to the local clock buffer at a target frequency such that a first timing constraint may be met. The operation performed by the logic synthesis tool forms a determined clock control signal input. Responsive to the logic synthesis tool determining the determined clock control signal input, the logic synthesis tool couples the local clock buffer to the determined clock control signal input that drives the clock control signal to the local clock buffer at the target frequency to achieve timing closure in the clocked logic circuit.
    Type: Grant
    Filed: July 3, 2007
    Date of Patent: July 12, 2011
    Assignee: International Business Machines Corporation
    Inventors: Lawrence D. Curley, John M. Isakson, Arjen Mets, Travis W. Pouarz, Thomas E. Rosser, Kristen M. Tucker
  • Efficient Utilization of a Multi-Source Network of Control Logic to Achieve Timing Closure in a Clocked Logic Circuit
    Publication number: 20090013206
    Abstract: A method, system, and computer program product are provided for achieving timing closure in a clocked logic circuit. For each local clock buffer in a set of local clock buffers, a logic synthesis tool determines a clock control signal input from a set of clock control signal inputs that will drive a clock control signal to the local clock buffer at a target frequency such that a first timing constraint may be met. The operation performed by the logic synthesis tool forms a determined clock control signal input. Responsive to the logic synthesis tool determining the determined clock control signal input, the logic synthesis tool couples the local clock buffer to the determined clock control signal input that drives the clock control signal to the local clock buffer at the target frequency to achieve timing closure in the clocked logic circuit.
    Type: Application
    Filed: July 3, 2007
    Publication date: January 8, 2009
    Inventors: Lawrence D. Curley, John M. Isakson, Arjen Mets, Travis W. Pouarz, Thomas E. Rosser, Kristen M. Tucker