Abstract: In an aspect, a pipelined execution resource can produce an intermediate result for use in an iterative approximation algorithm in an odd number of clock cycles. The pipelined execution resource executes SIMD requests by staggering commencement of execution of the requests from a SIMD instruction. When executing one or more operations for a SIMD iterative approximation algorithm, and an operation for another SIMD iterative approximation algorithm is ready to begin execution, control logic causes intermediate results completed by the pipelined execution resource to pass through a wait state, before being used in a subsequent computation. This wait state presents two open scheduling cycles in which both parts of the next SIMD instruction can begin execution. Although the wait state increases latency to complete an in-progress algorithm, a total throughput of execution on the pipeline increases.

Abstract: In an aspect, a pipelined execution resource can produce an intermediate result for use in an iterative approximation algorithm in an odd number of clock cycles. The pipelined execution resource executes SIMD requests by staggering commencement of execution of the requests from a SIMD instruction. When executing one or more operations for a SIMD iterative approximation algorithm, and an operation for another SIMD iterative approximation algorithm is ready to begin execution, control logic causes intermediate results completed by the pipelined execution resource to pass through a wait state, before being used in a subsequent computation. This wait state presents two open scheduling cycles in which both parts of the next SIMD instruction can begin execution. Although the wait state increases latency to complete an in-progress algorithm, a total throughput of execution on the pipeline increases.

Abstract: In an aspect, a pipelined execution resource can produce an intermediate result for use in an iterative approximation algorithm in an odd number of clock cycles. The pipelined execution resource executes SIMD requests by staggering commencement of execution of the requests from a SIMD instruction. When executing one or more operations for a SIMD iterative approximation algorithm, and an operation for another SIMD iterative approximation algorithm is ready to begin execution, control logic causes intermediate results completed by the pipelined execution resource to pass through a wait state, before being used in a subsequent computation. This wait state presents two open scheduling cycles in which both parts of the next SIMD instruction can begin execution. Although the wait state increases latency to complete an in-progress algorithm, a total throughput of execution on the pipeline increases.

Abstract: In an aspect, a pipelined execution resource can produce an intermediate result for use in an iterative approximation algorithm in an odd number of clock cycles. The pipelined execution resource executes SIMD requests by staggering commencement of execution of the requests from a SIMD instruction. When executing one or more operations for a SIMD iterative approximation algorithm, and an operation for another SIMD iterative approximation algorithm is ready to begin execution, control logic causes intermediate results completed by the pipelined execution resource to pass through a wait state, before being used in a subsequent computation. This wait state presents two open scheduling cycles in which both parts of the next SIMD instruction can begin execution. Although the wait state increases latency to complete an in-progress algorithm, a total throughput of execution on the pipeline increases.

Abstract: A waveform compression and display technique saves both a peak detected version (background version) and a decimated/lowpass filtered version (foreground version) of a sampled electrical signal. The two versions are displayed simultaneously overlaid together in a contrasting manner so as not to obscure information contained in either of them. The lowpass filtered version uses a series of simple lowpass filters with decimation to produce a single data stream from a plurality of data streams derived from the sampled electrical signal. The single data stream may then be subjected to additional filtering, such as a cascaded integrator-comb filter, to obtain a desired frequency bandwidth. When displayed, the peak detect pixels adjacent the decimated/lowpass filtered pixels may be adjusted in intensity so that the low frequency information of the lowpass filtered waveform is not lost, while the peak detect pixels further from the lowpass filtered pixels are intensified to highlight the high frequency information.

Abstract: A “no dead time” data acquisition system for a measurement instrument receives a digitized signal representing an electrical signal being monitored and generates from the digitized signal a trigger signal using a fast digital trigger circuit, the trigger signal including all trigger events within the digitized signal. The digitized signal is compressed as desired and delayed by a first-in, first-out (FIFO) buffer for a period of time to assure a predetermined amount of data prior to a first trigger event in the trigger signal. The delayed digitized signal is delivered to a fast rasterizer or drawing engine upon the occurrence of the first trigger event to generate a waveform image. The waveform image is then provided to a display buffer for combination with prior waveforms and/or other graphic inputs from other drawing engines. The contents of the display buffer are provided to a display at a display update rate to show a composite of all waveform images representing the electrical signal.

Abstract: A noise rejection filter for a trigger circuit uses an algorithm that updates the filter output monotonically so long as the signal slope remains unchanged, maintains the filter output at a constant level when the signal slope changes but the difference between the sample value and the filter output is less than or equal to a hysteresis value, and changes the signal slope while updating the filter output when the difference is greater than the hysteresis value. This maintains the peaks of the input signal at the filter output. The noise rejection filter may be used in a trigger circuit prior to a comparator so that the trigger signal from the comparator accurately reflects the signal pulse width at a desired trigger level and trigger events are detected when the desired trigger level is near the peaks of the input signal.

Abstract: A noise rejection filter for a trigger circuit uses an algorithm that updates the filter output monotonically so long as the signal slope remains unchanged, maintains the filter output at a constant level when the signal slope changes but the difference between the sample value and the filter output is less than or equal to a hysteresis value, and changes the signal slope while updating the filter output when the difference is greater than the hysteresis value. This maintains the peaks of the input signal at the filter output. The noise rejection filter may be used in a trigger circuit prior to a comparator so that the trigger signal from the comparator accurately reflects the signal pulse width at a desired trigger level and trigger events are detected when the desired trigger level is near the peaks of the input signal.

Abstract: A method of characterizing a newly acquired waveform with respect to previously acquired waveforms during monitoring of a generally repetitive signal, where the previously acquired waveforms have been rasterized into a two-dimensional array of memory locations, reads history values for those memory locations associated with an active portion of the newly acquired waveform, compares the history values with history value ranges, increments a count for one of a plurality of recent pixel counters corresponding to the history value ranges, each counter having a different history value range, and modifies the history values in the memory locations. From the counts accumulated for each of the history value ranges the variability of the newly acquired waveform from the generally repetitive signal is determined.

Abstract: An improved digital trigger circuit has a plurality of data samples extracted from an input electrical signal for each sample clock cycle. The plurality of data samples are compared in parallel with a high threshold level and a low threshold level which provides hysteresis for noise rejection. Also the plurality of data samples are used to determine sub-sample trigger positioning. The comparison outputs are input to a digital trigger logic circuit for identifying a selected trigger event and generating a trigger for the acquisition of data from the input electrical signal for analysis and display. The digital trigger logic provides edge event triggering, pulse width triggering and transition time triggering, among others.

Abstract: A “no dead time” data acquisition system for a measurement instrument receives a digitized signal representing an electrical signal being monitored and generates from the digitized signal a trigger signal using a fast digital trigger circuit, the trigger signal including all trigger events within the digitized signal. The digitized signal is compressed as desired and delayed by a first-in, first-out (FIFO) buffer for a period of time to assure a predetermined amount of data prior to a first trigger event in the trigger signal. The delayed digitized signal is delivered to a fast rasterizer or drawing engine upon the occurrence of the first trigger event to generate a waveform image. The waveform image is then provided to a display buffer for combination with prior waveforms and/or other graphic inputs from other drawing engines. The contents of the display buffer are provided to a display at a display update rate to show a composite of all waveform images representing the electrical signal.

Abstract: An improved digital trigger circuit has a plurality of data samples extracted from an input electrical signal for each sample clock cycle. The plurality of data samples are compared in parallel with a high threshold level and a low threshold level which provides hysteresis for noise rejection. Also the plurality of data samples are used to determine sub-sample trigger positioning. The comparison outputs are input to a digital trigger logic circuit for identifying a selected trigger event and generating a trigger for the acquisition of data from the input electrical signal for analysis and display. The digital trigger logic provides edge event triggering, pulse width triggering and transition time triggering, among others.

Abstract: A waveform compression and display technique saves both a peak detected version (background version) and a decimated/lowpass filtered version (foreground version) of a sampled electrical signal. The two versions are displayed simultaneously overlaid together in a contrasting manner so as not to obscure information contained in either of them. The lowpass filtered version uses a series of simple lowpass filters with decimation to produce a single data stream from a plurality of data streams derived from the sampled electrical signal. The single data stream may then be subjected to additional filtering, such as a cascaded integrator-comb filter, to obtain a desired frequency bandwidth. When displayed, the peak detect pixels adjacent the decimated/lowpass filtered pixels may be adjusted in intensity so that the low frequency information of the lowpass filtered waveform is not lost, while the peak detect pixels further from the lowpass filtered pixels are intensified to highlight the high frequency information.

Abstract: A method of characterizing a newly acquired waveform with respect to previously acquired waveforms during monitoring of a generally repetitive signal, where the previously acquired waveforms have been rasterized into a two-dimensional array of memory locations, reads history values for those memory locations associated with an active portion of the newly acquired waveform, compares the history values with history value ranges, increments a count for one of a plurality of recent pixel counters corresponding to the history value ranges, each counter having a different history value range, and modifies the history values in the memory locations. From the counts accumulated for each of the history value ranges the variability of the newly acquired waveform from the generally repetitive signal is determined.