Patents by Inventor Kristin De Meyer

Kristin De Meyer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multiple gate semiconductor device and method for forming same
    Patent number: 7202517
    Abstract: A multiple gate semiconductor device. The device includes at least two gates. The dopant distribution in the semiconductor body of the device varies from a low value near the surface of the body towards a higher value inside the body of the device.
    Type: Grant
    Filed: July 16, 2004
    Date of Patent: April 10, 2007
    Assignee: Interuniversitair Microelektronica Centrum (IMEC vzw)
    Inventors: Abhisek Dixit, Kristin De Meyer
  • Integrated semiconductor fin device and a method for manufacturing such device
    Patent number: 6974729
    Abstract: A CMOS circuit for and method of forming a FinFET device is disclosed. The method includes providing a substrate comprising a semiconductor layer, forming on the semiconductor layer active areas insulated from each other by field areas, forming at least one dummy gate on at least one of said active areas and forming source and drain regions on the at least one of the active areas. The method also includes covering the substrate with an insulating layer leaving said dummy gate exposed and forming an open cavity by patterning the dummy gate to form a dummy fin and a semiconductor fin aligned to said dummy fin, both fins extending from the source to the drain regions.
    Type: Grant
    Filed: July 15, 2003
    Date of Patent: December 13, 2005
    Assignee: Interuniversitair Microelektronica Centrum (IMEC)
    Inventors: Nadine Collaert, Kristin De Meyer
  • Integrated semiconductor fin device and a method for manufacturing such device
    Publication number: 20050020020
    Abstract: A CMOS circuit for and method of forming a FinFET device is disclosed. The method includes providing a substrate comprising a semiconductor layer, forming on the semiconductor layer active areas insulated from each other by field areas, forming at least one dummy gate on at least one of said active areas and forming source and drain regions on the at least one of the active areas. The method also includes covering the substrate with an insulating layer leaving said dummy gate exposed and forming an open cavity by patterning the dummy gate to form a dummy fin and a semiconductor fin aligned to said dummy fin, both fins extending from the source to the drain regions.
    Type: Application
    Filed: July 15, 2003
    Publication date: January 27, 2005
    Inventors: Nadine Collaert, Kristin De Meyer