Abstract: Embodiments of the present disclosure support a simulation of a plurality of processor core models. The processor core models are executed in parallel within a sliding time window of a defined size. Each processor core model is executed in a different corresponding thread and advances a local core time within the sliding time window. The sliding time window advances by updating a start time of the sliding time window based on the local core time of each processor core model. One or more hardware models and a simulation kernel are executed in a separate thread having a simulation time and simulation events. The start time of the sliding time window is updated based further on an event time of a next event of the simulation events scheduled in the separate thread.

Abstract: Embodiments of the present disclosure support a simulation of a plurality of processor core models. The processor core models are executed in parallel within a sliding time window of a defined size. Each processor core model is executed in a different corresponding thread and advances a local core time within the sliding time window. The sliding time window advances by updating a start time of the sliding time window based on the local core time of each processor core model. One or more hardware models and a simulation kernel are executed in a separate thread having a simulation time and simulation events. The start time of the sliding time window is updated based further on an event time of a next event of the simulation events scheduled in the separate thread.