Patents by Inventor Kristof Darmawikarta

Kristof Darmawikarta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250253245
    Abstract: A die interconnect substrate comprises a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate comprises a multilayer substrate structure comprising a substrate interconnect. The bridge die is embedded in the multilayer substrate structure. The substrate interconnect extends from a level above the bridge die to a level below the bridge die. The multilayer substrate structure further comprises an electrically insulating layer comprising a first electrically insulating material. The multilayer substrate structure further comprises an electrically insulating filler structure located laterally between the bridge die and the electrically insulating layer, wherein the electrically insulating filler structure comprises a second electrically insulating material different from the first electrically insulating material.
    Type: Application
    Filed: April 18, 2025
    Publication date: August 7, 2025
    Inventors: Robert Alan MAY, Kristof DARMAWIKARTA, Sri Ranga Sai Sai BOYAPATI
  • Patent number: 12354931
    Abstract: The present disclosure is directed to semiconductor dies and methods that provide a glass substrate, a pulsed laser tool to produce a line-shaped modification to the glass substrate for forming a plurality of structures in the glass substrate. The pulse laser tool may be provided with a predetermined pattern for its movement. The predetermined pattern moves the pulsed laser tool in a series of single steps in a first axial direction and in a series of plural lateral steps in a second axial direction that is perpendicular to the first axial direction, in particular, the single step is followed by the plural lateral steps in a repeating sequence. The series of plural lateral steps form an assembly of line-shaped modifications in parallel rows on the glass substrate, and thereafter the plurality of structures may be formed from the parallel rows of line-shaped modifications in the glass substrate.
    Type: Grant
    Filed: May 6, 2022
    Date of Patent: July 8, 2025
    Assignee: Intel Corporation
    Inventors: Vinith Bejugam, Kristof Darmawikarta, Yonggang Li, Samuel George, Srinivas Pietambaram
  • Patent number: 12353070
    Abstract: An electro-optical system having one or more electro-optical devices integrally formed within a substrate and associated methods are disclosed. An electro-optical system including an electro-optic switch is shown. An electro-optical system including an electro-optic modulator is shown. An electro-optical system including an optical resonator is shown.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: July 8, 2025
    Assignee: Intel Corporation
    Inventors: Hiroki Tanaka, Brandon C Marin, Kristof Darmawikarta, Srinivas Venkata Ramanuja Pietambaram, Jeremy D Ecton, Hari Mahalingam, Benjamin Duong
  • Patent number: 12354883
    Abstract: Various embodiments disclosed relate to methods of making omni-directional semiconductor interconnect bridges. The present disclosure includes semiconductor assemblies including a mold layer having mold material, a first filler material dispersed in the mold material, and a second filler material dispersed in the mold material, wherein the second filler material is heterogeneously dispersed.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: July 8, 2025
    Assignee: Intel Corporation
    Inventors: Bohan Shan, Dingying Xu, Kristof Darmawikarta, Srinivas Venkata Ramanuja Pietambaram, Hongxia Feng, Gang Duan, Jung Kyu Han, Xiaoying Guo, Jeremy D. Ecton, Santosh Tripathi, Bai Nie, Haobo Chen, Kyle Jordan Arrington, Yue Deng, Wei Wei
  • Patent number: 12354963
    Abstract: Embodiments include an electronic package with an embedded multi-interconnect bridge (EMIB) and methods of making such packages. Embodiments include a first layer, that is an organic material and a second layer disposed over the first layer. In an embodiment, a cavity is formed through the second layer to expose a first surface of the first layer. A bridge substrate is in the cavity and is supported by the first surface of the first layer. Embodiments include a first die over the second layer that is electrically coupled to a first contact on the bridge substrate, and a second die over the second layer that is electrically coupled to a second contact on the bridge substrate. In an embodiment the first die is electrically coupled to the second die by the bridge substrate.
    Type: Grant
    Filed: March 29, 2024
    Date of Patent: July 8, 2025
    Assignee: Intel Corporation
    Inventors: Kristof Darmawikarta, Hiroki Tanaka, Robert May, Sameer Paital, Bai Nie, Jesse Jones, Chung Kwang Christopher Tan
  • Publication number: 20250216608
    Abstract: Technologies for micro-LED optical communication via glass waveguides are disclosed. In an illustrative embodiment, a glass interposer is mounted on a circuit board, and several integrated circuit (IC) dies are positioned above the glass interposer. A micro-LED assembly is mounted on each of the IC dies. Waveguides defined in the glass interposer can carry light between the micro-LED assemblies of the various IC dies, providing a high-bandwidth connection between the IC dies. The micro-LED assemblies can provide low-power, high-bandwidth connectivity between the IC dies and can operate in the high-temperature environment near the IC dies.
    Type: Application
    Filed: December 28, 2023
    Publication date: July 3, 2025
    Inventors: Benjamin T. Duong, Khaled Ahmed, Kristof Darmawikarta, Stephen Morein, Bai Nie
  • Publication number: 20250216636
    Abstract: Embodiments disclosed herein include photonics packages. In an embodiment, the photonics package comprises a substrate. In an embodiment, a first interposer is over the substrate, and a first die is on the first interposer. In an embodiment, a second interposer is over the substrate, and a second die is on the second interposer. In an embodiment, an optical bridge is between the first interposer and the second interposer.
    Type: Application
    Filed: June 27, 2022
    Publication date: July 3, 2025
    Inventors: Vinod ADIVARAHAN, Liqiang CUI, Kristof DARMAWIKARTA, Gang DUAN, Benjamin DUONG, Shereen ELHALAWATY, Sandeep GAAN, Brandon C. MARIN, Srinivas V. PIETAMBARAM, Marcel SAID
  • Publication number: 20250218678
    Abstract: An apparatus comprises a substrate core comprising a hole extending from an opening at a first surface of the substrate core to a second surface opposite the first surface. A metal layer is over the first surface. The metal layer comprises a plurality of first metal features over a first portion of the opening. The metal layer also includes a second metal feature extending from a sidewall of the hole and over a second portion of the opening. A die is within the hole and coupled to the first metal features by solder features. The die may comprise a capacitor.
    Type: Application
    Filed: December 28, 2023
    Publication date: July 3, 2025
    Applicant: Intel Corporation
    Inventors: Hiroki Tanaka, Kristof Darmawikarta, Robert May, Bai Nie, Bohan Shan, Gang Duan, Srinivas Pietambaram
  • Patent number: 12347788
    Abstract: Glass substrates having signal shielding for use with semiconductor packages and related methods are disclosed. An example semiconductor package includes a core layer defining a channel and a through glass via (TGV). The channel at least partially surrounding the TGV. A signal transmission line is provided in the opening and extending through the core layer. An electrically conductive material positioned in the channel. The conductive material to provide electromagnetic shielding to the transmission line.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: July 1, 2025
    Assignee: Intel Corporation
    Inventors: Kristof Darmawikarta, Srinivas V. Pietambaram, Kemal Aygun, Telesphor Kamgaing, Zhiguo Qian, Jiwei Sun
  • Patent number: 12345932
    Abstract: Various embodiments disclosed relate to photonic assemblies. The present disclosure includes methods for packaging a photonic assembly, including attaching a bridge die to a glass substrate, attaching an electronic integrated circuit die to the glass substrate and the bridge die, attaching a photonic integrated circuit die to the glass substrate and the bridge die, bonding a coupling adapter to the glass substrate and in situ forming a waveguide in the coupling adapted, the waveguide aligning with the photonic integrated circuit die.
    Type: Grant
    Filed: September 23, 2021
    Date of Patent: July 1, 2025
    Assignee: Intel Corporation
    Inventors: Bai Nie, Pooya Tadayon, Leonel R. Arana, Yonggang Li, Changhua Liu, Kristof Darmawikarta, Srinivas Venkata Ramanuja Pietambaram, Tarek A. Ibrahim, Hari Mahalingam, Benjamin Duong
  • Patent number: 12349282
    Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed to embedding capacitors in through glass vias within a glass core of a substrate. In embodiments, the through glass vias may extend entirely from a first side of the glass core to a second side of the glass core opposite the first side. Layers of electrically conductive material and dielectric material may then be deposited within the through glass via to form a capacitor. the capacitor may then be electrically coupled with electrical routings on buildup layers on either side of the glass core. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: September 22, 2021
    Date of Patent: July 1, 2025
    Assignee: Intel Corporation
    Inventors: Benjamin Duong, Aleksandar Aleksov, Helme A. Castro De La Torre, Kristof Darmawikarta, Darko Grujicic, Sashi S. Kandanur, Suddhasattwa Nad, Srinivas V. Pietambaram, Rengarajan Shanmugam, Thomas L. Sounart, Marcel Wall
  • Publication number: 20250201485
    Abstract: Apparatuses, capacitor modules, assemblies, and techniques related to package substrate embedded capacitors are described. A capacitor module is formed by fabricating capacitor structures along a surface of one or more substrates, cutting the capacitor structures from the one or more substrates and stacking the resultant capacitor structures and substrates into a capacitor module. The capacitor module is then vertically embedded in a package substrate or core.
    Type: Application
    Filed: December 14, 2023
    Publication date: June 19, 2025
    Applicant: Intel Corporation
    Inventors: Hiroki Tanaka, Srinivas Pietambaram, Robert May, Kristof Darmawikarta, Aleksandar Aleksov, Bohan Shan, Gang Duan
  • Patent number: 12334443
    Abstract: Embodiments include an electronic package with an embedded multi-interconnect bridge (EMIB) and methods of making such packages. Embodiments include a first layer, that is an organic material and a second layer disposed over the first layer. In an embodiment, a cavity is formed through the second layer to expose a first surface of the first layer. A bridge substrate is in the cavity and is supported by the first surface of the first layer. Embodiments include a first die over the second layer that is electrically coupled to a first contact on the bridge substrate, and a second die over the second layer that is electrically coupled to a second contact on the bridge substrate. In an embodiment the first die is electrically coupled to the second die by the bridge substrate.
    Type: Grant
    Filed: February 6, 2024
    Date of Patent: June 17, 2025
    Assignee: Intel Corporation
    Inventors: Kristof Darmawikarta, Hiroki Tanaka, Robert May, Sameer Paital, Bai Nie, Jesse Jones, Chung Kwang Christopher Tan
  • Patent number: 12334447
    Abstract: Embodiments described herein relate to lithographically defined vertical interconnect accesses (litho-vias) for a bridge die first level interconnect (FLI) and techniques of fabricating such litho-vias. In one example, a package substrate comprises a bridge die embedded in the package substrate; a first contact pad outside a perimeter of the bridge die; a second contact pad inside the perimeter of the bridge die and coupled to the bridge die by a first via; a third pad inside the perimeter of the bridge die, adjacent to the second contact pad, and coupled to the bridge die by a second via. The first contact pad has a surface finish disposed thereon. A first protruded interconnect structure is positioned on the first via and a second protruded interconnect structure is positioned on the second via. Each of the first and second vias have sidewalls that are substantially vertical.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: June 17, 2025
    Inventors: Kristof Darmawikarta, Tarek Ibrahim, Siddharth Alur, Rahul Jain, Haobo Chen
  • Publication number: 20250183179
    Abstract: Embodiments disclosed herein comprise bridge dies with embedded passive components. In an embodiment, the bridge die is an apparatus that comprises a substrate with a via at least partially through a thickness of the substrate. In an embodiment, the via is electrically conductive. In an embodiment, a shell is provided around a perimeter of the via, and the shell is a different material than the via.
    Type: Application
    Filed: December 4, 2023
    Publication date: June 5, 2025
    Inventors: Brandon C. MARIN, Mohamed R. SABER, Srinivas Venkata Ramanuja PIETAMBARAM, Gang DUAN, Jeremy D. ECTON, Suddhasattwa NAD, Benjamin DUONG, Bohan SHAN, Sashi S. KANDANUR, Cary KULIASHA, Shruti SHARMA, Mollie STEWART, Rahul N. MANEPALLI, Kristof DARMAWIKARTA
  • Patent number: 12300620
    Abstract: A glass substrate houses an embedded multi-die interconnect bridge that is part of a semiconductor device package. Through-glass vias communicate to a surface for mounting on a semiconductor package substrate.
    Type: Grant
    Filed: September 12, 2023
    Date of Patent: May 13, 2025
    Assignee: Intel Corporation
    Inventors: Srinivas V. Pietambaram, Tarek Ibrahim, Kristof Darmawikarta, Rahul N. Manepalli, Debendra Mallik, Robert L. Sankman
  • Patent number: 12300613
    Abstract: A die interconnect substrate comprises a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate comprises a multilayer substrate structure comprising a substrate interconnect. The bridge die is embedded in the multilayer substrate structure. The substrate interconnect extends from a level above the bridge die to a level below the bridge die. The multilayer substrate structure further comprises an electrically insulating layer comprising a first electrically insulating material. The multilayer substrate structure further comprises an electrically insulating filler structure located laterally between the bridge die and the electrically insulating layer, wherein the electrically insulating filler structure comprises a second electrically insulating material different from the first electrically insulating material.
    Type: Grant
    Filed: November 30, 2023
    Date of Patent: May 13, 2025
    Assignee: Intel Corporation
    Inventors: Robert Alan May, Kristof Darmawikarta, Sri Ranga Sai Sai Boyapati
  • Publication number: 20250125275
    Abstract: An apparatus is provided which comprises: a plurality of first conductive contacts having a first pitch spacing on a substrate surface, a plurality of second conductive contacts having a second pitch spacing on the substrate surface, and a plurality of conductive interconnects disposed within the substrate to couple a first grouping of the plurality of second conductive contacts associated with a first die site with a first grouping of the plurality of second conductive contacts associated with a second die site and to couple a second grouping of the plurality of second conductive contacts associated with the first die site with a second grouping of the plurality of second conductive contacts associated with the second die site, wherein the conductive interconnects to couple the first groupings are present in a layer of the substrate above the conductive interconnects to couple the second groupings. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: December 23, 2024
    Publication date: April 17, 2025
    Inventors: Aleksandar ALEKSOV, Adel A. ELSHERBINI, Kristof DARMAWIKARTA, Robert A. MAY, Sri Ranga Sai BOYAPATI
  • Publication number: 20250125277
    Abstract: A foundation layer and methods of forming a conductive via are described. A die pad is formed over a die. A seed layer is deposited over the die pad and the foundation layer. A first photoresist layer is deposited over the seed layer, and the first layer is patterned to form a conductive line opening over the die pad. A conductive material is deposited into the conductive line opening to form a conductive line. A second photoresist layer is deposited over the first layer, and the second layer is patterned to form a via opening over the conductive line. The conductive material is deposited into the via opening to form the conductive via, where the conductive material only deposits on portions of exposed conductive line. The second and first layers are removed. Portions of exposed seed layer are recessed, and then a top surface of the conductive via is exposed.
    Type: Application
    Filed: December 23, 2024
    Publication date: April 17, 2025
    Inventors: Srinivas V. PIETAMBARAM, Sri Ranga Sai BOYAPATI, Robert A. MAY, Kristof DARMAWIKARTA, Javier SOTO GONZALEZ, Kwangmo LIM
  • Publication number: 20250118647
    Abstract: An electronic package includes an interposer having an interposer substrate, a cavity that passes into but not through the interposer substrate, a through interposer via (TIV) within the interposer substrate, and an interposer pad electrically coupled to the TIV. The electronic package includes a nested component in the cavity, wherein the nested component includes a component pad coupled to a through-component via. A core via is beneath the nested component, the core via extending from the nested component through the interposer substrate. A die is coupled to the interposer pad by a first interconnect and coupled to the component pad by a second interconnect.
    Type: Application
    Filed: December 19, 2024
    Publication date: April 10, 2025
    Inventors: Srinivas V. PIETAMBARAM, Debendra MALLIK, Kristof DARMAWIKARTA, Ravindranath V. MAHAJAN, Rahul N. MANEPALLI