Abstract: A circular buffer architecture includes a memory coupled to a producer circuit and a consumer circuit. The memory is configured to store objects. The memory can include memory banks. The number of the memory banks is less than a number of the objects. The circular buffer can include hardware locks configured to reserve selected ones of the memory banks for use by the producer circuit or the consumer circuit. The circular buffer can include a buffer controller coupled to the memory and configured to track a plurality of positions. The positions can include a consumer bank position, a consumer object position, a producer bank position, and a producer object position. The buffer controller is configured to allocate selected ones of the objects from the memory banks to the producer circuit and to the consumer circuit according to the tracked positions and using the hardware locks.

Abstract: A circular buffer architecture includes a memory coupled to a producer circuit and a consumer circuit. The memory is configured to store objects. The memory can include memory banks. The number of the memory banks is less than a number of the objects. The circular buffer can include hardware locks configured to reserve selected ones of the memory banks for use by the producer circuit or the consumer circuit. The circular buffer can include a buffer controller coupled to the memory and configured to track a plurality of positions. The positions can include a consumer bank position, a consumer object position, a producer bank position, and a producer object position. The buffer controller is configured to allocate selected ones of the objects from the memory banks to the producer circuit and to the consumer circuit according to the tracked positions and using the hardware locks.

Abstract: An example a method of optimizing a neural network having a plurality of layers includes: obtaining an architecture constraint for circuitry of an inference platform that implements the neural network; training the neural network on a training platform to generate network parameters and feature maps for the plurality of layers; and constraining the network parameters, the feature maps, or both based on the architecture constraint.

Abstract: An integrated circuit (IC) can include a decomposer data mover circuit configured to read sub-arrays from array data stored in a source memory; generate metadata headers for the sub-arrays, wherein each metadata header includes location information indicating location of a corresponding sub-array within the array data; create data tiles, wherein each data tile includes a sub-array and a corresponding metadata header; and output the data tiles to compute circuitry within the IC. The IC can include a composer data mover circuit configured to receive processed versions of the data tiles from the compute circuitry; extract valid data regions from the processed versions of the data tiles; and write the valid data regions to a destination memory based on the location information from the metadata headers of the processed versions of the data tiles.

Abstract: An example method of training a neural network includes defining hardware building blocks (HBBs), neuron equivalents (NEQs), and conversion procedures from NEQs to HBBs; defining the neural network using the NEQs in a machine learning framework; training the neural network on a training platform; and converting the neural network as trained into a netlist of HBBs using the conversion procedures to convert the NEQs in the neural network to the HBBs of the netlist.

Abstract: An example method of implementing a neural network includes selecting a first neural network architecture from a search space and training the neural network having the first neural network architecture to obtain an accuracy and an implementation cost. The implementation cost is based on a programmable device of an inference platform. The method further includes selecting a second neural network architecture from the search space based on the accuracy and the implementation cost, and outputting weights and hyperparameters for the neural network having the second neural network architecture.

Abstract: An example a method of optimizing a neural network having a plurality of layers includes: obtaining an architecture constraint for circuitry of an inference platform that implements the neural network; training the neural network on a training platform to generate network parameters and feature maps for the plurality of layers; and constraining the network parameters, the feature maps, or both based on the architecture constraint.

Abstract: Digital signal processing and, more particularly, digital video coding is described. Video encoding or decoding of frames includes accessing a plurality of values that can include at least one quantized DC default value and a plurality of quantized DC block values for neighboring blocks with respect to an intra block. A direction of change for the intra block is determined using predictor values obtained from the accessed values.

Abstract: Methods and devices for encoding and decoding video data are provided, wherein an image data structure can be represented as a group of macroblocks and each macroblock contains a plurality of blocks. One inventive aspect includes a method of decoding image data comprises decoding a current block of data, comprising retrieving a related reference block, decoding texture information of the current block, and reconstructing the current block, prior to the decoding of another block of data.

Abstract: Methods and devices for encoding and decoding video data are provided, wherein an image data structure can be represented as a group of macroblocks and each macroblock contains a plurality of blocks. One aspect of the invention includes a method of decoding image data comprises decoding a current block of data, comprising retrieving a related reference block, decoding texture information of the current block, and reconstructing the current block, prior to the decoding of another block of data.