Abstract: An example apparatus includes a phase detector and a phase error detector. The phase detector may set a status signal to indicate status of phase difference between a reference clock and a feedback clock, the feedback clock generated by a clock tracking circuit to track the reference clock. The phase error detector may set an error signal to be proportional to a phase difference between the reference clock and the feedback clock. At least partially responsive to the status signal, the phase error detector to change from triggered only by edges of the reference clock and feedback clock having a first polarity to triggered by edges of the reference clock and feedback clock having the first polarity and by edges of the reference clock and feedback clock having a second polarity, the second polarity different than the first polarity.

Abstract: An example apparatus includes a phase detector, a digital discriminator, and a logic circuit. A status signal of the phase detector is at least partially based on a phase relationship between a reference clock and a feedback clock, the feedback clock generated by a clock tracking circuit to track the reference clock. The digital discriminator may sample the status signal of the phase detector. The logic circuit may determine a locked status of the clock tracking circuit at least partially based on samples of the status signal of the phase detector.

Abstract: A method includes: observing that a digitally controlled oscillator (DCO) frequency is at a boundary of a DCO frequency overlap region; and bypassing at least a portion of the DCO frequency overlap region.

Abstract: One or more examples relate to a method. The method includes: receiving up/down error signals indicative of duty cycle mismatch between a reference clock signal and a changed feedback clock signal that represents an output clock signal generated by a clock tracking circuit to track the reference clock signal; setting a duty cycle of a changed feedback clock signal to reduce duty cycle mismatch indicated by the up/down error signals; and providing the changed feedback clock having set duty cycle.

Abstract: One or more examples relate to a method. The method may include: comparing a first value and a second value, the first value representing a duty cycle of a reference clock and the second value representing a duty cycle of an output clock generated by a clock tracking circuit to track the reference clock; setting a duty cycle of a changed clock to reduce duty cycle mismatch between the reference clock and the output clock indicated by the comparing; and providing the changed clock having set duty cycle in lieu of the one of the reference clock or the output clock.

Abstract: One or more examples relate to triggering a single error detector on rising and falling edges of clock signals, and generating an error signal therefrom. A method may include receiving a first clock signal and a second clock signal. The method may include generating, via a single error detector being triggered at least partially responsive to like respective edges of the first clock signal and the second clock signal, an error signal that represents a phase difference between the first clock signal and the second clock signal.

Abstract: Embodiments of the invention include an integrated circuit including a line driver. The integrated circuit includes a voltage mode driver comprising complementary first and second input voltage drivers, a programmable resistor network and a current mode driver. The programmable resistor network allows the amplitude of the line driver outputs to be controlled based on the particular resistor connections in the programmable resistor network. Also, the differential impedance of the integrated circuit and the common mode impedance of the integrated circuit are based on the resistance values of the resistors in the programmable resistor network.

Abstract: Embodiments of the invention include an integrated circuit including a line driver. The integrated circuit includes a voltage mode driver comprising complementary first and second input voltage drivers, a programmable resistor network and a current mode driver. The programmable resistor network allows the amplitude of the line driver outputs to be controlled based on the particular resistor connections in the programmable resistor network. Also, the differential impedance of the integrated circuit and the common mode impedance of the integrated circuit are based on the resistance values of the resistors in the programmable resistor network.

Abstract: A circuit for measuring and compensating for DC offset introduced into a differential signal due to, for example, terminator mismatches and interconnect resistance, is described herein. The circuit includes a plurality of capacitors that store test values of a differential signal, a summer, a comparator, a digital counter, and an analog-to-digital converter. The summer sums signals from the plurality of capacitors and a dc offset correction signal from the analog-to-digital converter. A differential output from the summer is processed by the comparator to generate a binary output signal that is used to recursively modify the value of the dc offset correction signal until the dc offset correction signal stabilizes.

Abstract: DC offset introduced into a differential signal is compensated for by DC offset correction circuitry. The DC offset correction circuitry receives a known training pattern of alternating logic high and logic low levels (i.e., 10101010 etc.). In one embodiment, the received signal is integrated and the result compared to a predetermined reference level. The result of the comparison is used to adjust a DC offset correction value that is added to the received signal. This process is iteratively performed until successive results of the comparison indicate that the DC offset has been compensated for in another embodiment, the duty-cycle of the received signal is calculated. The result of the duty-cycle calculation is used to iteratively adjust the DC offset correction value.

Abstract: DC offset introduced into a differential signal is compensated for by DC offset correction circuitry. The DC offset correction circuitry receives a known training pattern of alternating logic high and logic low levels (i.e., 10101010 etc.). In one embodiment, the received signal is integrated and the result compared to a predetermined reference level. The result of the comparison is used to adjust a DC offset correction value that is added to the received signal. This process is iteratively performed until successive results of the comparison indicate that the DC offset has been compensated for. In another embodiment, the duty-cycle of the received signal is calculated. The result of the duty-cycle calculation is used to iteratively adjust the DC offset correction value.

Abstract: A tunnel multiconnect system comprising a substrate of flexible dielectric material, a plurality of at least three first line conductors supported on the substrate to form a multiconductor pattern, a second conductor shaped to form a ground plane, a structure for mechanically positioning the second conductor in spaced relation to the multiconductor pattern to form a tunnel therebetween, and connectors located at each end of the first conductors for coupling the first conductors and the ground plane to respective multiport terminals of electrical subassemblies thereby forming a flexible high speed ribbon interconnect system.