Abstract: An elastic field programmable gate array (FPGA) system may include a plurality of FPGA devices connected in a physical ring topology. Each FPGA device may include a user programmable logic partition and a platform logic partition. The platform logic for each FPGA device can be selected by the client from a plurality of platform logic designs having progressively fewer components. Each platform logic design can include a platform management control block coupled to a microcontroller to implement device management functions and programming of the FPGA device. The size of the user programmable logic partition and the amount of available FPGA resources can vary for each FPGA device based on the platform logic design selected for that FPGA device.

Abstract: A programmable integrated circuit (IC) device can include memory isolation logic to isolate a memory device to retain the data stored in the memory device during a partial reconfiguration of the IC device. The memory isolation logic can isolate the memory device after receiving an isolation request to retain the data in the memory device, and de-isolate the memory device after receiving a de-isolation request when the reconfiguration of the user programmable logic is completed. Isolating the memory device may include invalidating memory requests from user programmable logic in the IC device and de-isolating may include providing the user programmable logic access to the memory device.