Abstract: The present invention is generally directed to a system for controlling placement of nanoparticles, and methods of using same. In one illustrative embodiment, the device includes a substrate and a plurality of funnels in the substrate, wherein each of the funnels comprises an inlet opening and an elongated, rectangular shaped outlet opening. In one illustrative embodiment, the method includes creating a dusty plasma comprising a plurality of carbon nanotubes, positioning a mask between the dusty plasma and a desired target for the carbon nanotubes, the mask having a plurality of openings extending therethrough, and extinguishing the dusty plasma to thereby allow at least some of the carbon nanotubes in the dusty plasma to pass through at least some of the plurality of openings in the mask and land on the target.

Abstract: A method of etching trenches into silicon of a semiconductor substrate includes forming a mask over silicon of a semiconductor substrate, with the mask comprising trenches formed there-through. Plasma etching is conducted to form trenches into the silicon of the semiconductor substrate using the mask. In one embodiment, the plasma etching includes forming an etching plasma using precursor gases which include SF6, an oxygen-containing compound, and a nitrogen-containing compound. In one embodiment, the plasma etching includes an etching plasma which includes a sulfur-containing component, an oxygen-containing component, and NFx.

Abstract: The present invention is generally directed to a system for controlling placement of nanoparticles, and methods of using same. In one illustrative embodiment, the device includes a substrate and a plurality of funnels in the substrate, wherein each of the funnels comprises an inlet opening and an elongated, rectangular shaped outlet opening. In one illustrative embodiment, the method includes creating a dusty plasma comprising a plurality of carbon nanotubes, positioning a mask between the dusty plasma and a desired target for the carbon nanotubes, the mask having a plurality of openings extending therethrough, and extinguishing the dusty plasma to thereby allow at least some of the carbon nanotubes in the dusty plasma to pass through at least some of the plurality of openings in the mask and land on the target.

Abstract: The present invention is generally directed to a system for controlling placement of nanoparticles, and methods of using same. In one illustrative embodiment, the device includes a substrate and a plurality of funnels in the substrate, wherein each of the funnels comprises an inlet opening and an elongated, rectangular shaped outlet opening. In one illustrative embodiment, the method includes creating a dusty plasma comprising a plurality of carbon nanotubes, positioning a mask between the dusty plasma and a desired target for the carbon nanotubes, the mask having a plurality of openings extending therethrough, and extinguishing the dusty plasma to thereby allow at least some of the carbon nanotubes in the dusty plasma to pass through at least some of the plurality of openings in the mask and land on the target.

Abstract: A method of etching trenches into silicon of a semiconductor substrate includes forming a mask over silicon of a semiconductor substrate, with the mask comprising trenches formed there-through. Plasma etching is conducted to form trenches into the silicon of the semiconductor substrate using the mask. In one embodiment, the plasma etching includes forming an etching plasma using precursor gases which include SF6, an oxygen-containing compound, and a nitrogen-containing compound. In one embodiment, the plasma etching includes an etching plasma which includes a sulfur-containing component, an oxygen-containing component, and NFx.

Abstract: The present invention is generally directed to a system for controlling placement of nanoparticles, and methods of using same. In one illustrative embodiment, the device includes a substrate and a plurality of funnels in the substrate, wherein each of the funnels comprises an inlet opening and an elongated, rectangular shaped outlet opening. In one illustrative embodiment, the method includes creating a dusty plasma comprising a plurality of carbon nanotubes, positioning a mask between the dusty plasma and a desired target for the carbon nanotubes, the mask having a plurality of openings extending therethrough, and extinguishing the dusty plasma to thereby allow at least some of the carbon nanotubes in the dusty plasma to pass through at least some of the plurality of openings in the mask and land on the target.

Abstract: A method of etching trenches into silicon of a semiconductor substrate includes forming a mask over silicon of a semiconductor substrate, with the mask comprising trenches formed there-through. Plasma etching is conducted to form trenches into the silicon of the semiconductor substrate using the mask. In one embodiment, the plasma etching includes forming an etching plasma using precursor gases which include SF6, an oxygen-containing compound, and a nitrogen-containing compound. In one embodiment, the plasma etching includes an etching plasma which includes a sulfur-containing component, an oxygen-containing component, and NFx.

Abstract: A voltage-controlled semiconductor inductor and method is provided. According to various embodiments, the voltage-controlled inductor includes a conductor configured with a number of inductive coils. The inductor also includes a semiconductor material having a contact with at least a portion of at least one of the coils. The semiconductor material is doped to form a diode with a first doped region of first conductivity type, a second doped region of second conductivity type, and a depletion region. A voltage across the diode changes lengths of the first doped region, the second doped region and the depletion region, and adjacent coils in contact with at least one of the doped regions are electrically shorted, thereby varying the inductance of the inductor. In various embodiments, the inductor is electrically connected to a resistor and a capacitor to provide a tunable RLC circuit. Other aspects and embodiments are provided herein.

Abstract: Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.

Abstract: A method of etching trenches into silicon of a semiconductor substrate includes forming a mask over silicon of a semiconductor substrate, with the mask comprising trenches formed there-through. Plasma etching is conducted to form trenches into the silicon of the semiconductor substrate using the mask. In one embodiment, the plasma etching includes forming an etching plasma using precursor gases which include SF6, an oxygen-containing compound, and a nitrogen-containing compound. In one embodiment, the plasma etching includes an etching plasma which includes a sulfur-containing component, an oxygen-containing component, and NFx.

Abstract: Nanoimprint lithography templates are provided. One such template includes a template base and a plurality of pattern layers of a first material. Each pattern layer is separated from an adjacent pattern layer by a spacing layer of a second material that is different from the first material. Such a template also includes a plurality of pillars of a third material that is different from the first material. Each of the pillars separates two adjacent pattern layers, and each of the pattern layers has a respective portion which protrudes from the spacing layers and from the pillars.

Abstract: A method of etching trenches into silicon of a semiconductor substrate includes forming a mask over silicon of a semiconductor substrate, with the mask comprising trenches formed there-through. Plasma etching is conducted to form trenches into the silicon of the semiconductor substrate using the mask. In one embodiment, the plasma etching includes forming an etching plasma using precursor gases which include SF6, an oxygen-containing compound, and a nitrogen-containing compound. In one embodiment, the plasma etching includes an etching plasma which includes a sulfur-containing component, an oxygen-containing component, and NFx.

Abstract: Methods for forming nanodots and/or a patterned material are provided. One such method involves forming a first patterning material over a base. Blades of a nanoimprint lithography template are placed within the first patterning material, wherein the blades extend along the base in a first direction. With the blades within the first patterning material, the first patterning material are cured. The blades are removed from the first patterning material to form a patterned first patterning material. The base is etched using the patterned first patterning material as a pattern to form openings in the base. The patterned first patterning material is removed from the base. A second patterning material is formed over the base and within the openings in the base. Blades of a nanoimprint lithography template are placed within the second patterning material, wherein the blades extend along the base in a second direction, which is generally perpendicular with respect to the first direction.

Abstract: Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.

Abstract: Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.

Abstract: A voltage-controlled semiconductor inductor and method is provided. According to various embodiments, the voltage-controlled inductor includes a conductor configured with a number of inductive coils. The inductor also includes a semiconductor material having a contact with at least a portion of at least one of the coils. The semiconductor material is doped to form a diode with a first doped region of first conductivity type, a second doped region of second conductivity type, and a depletion region. A voltage across the diode changes lengths of the first doped region, the second doped region and the depletion region, and adjacent coils in contact with at least one of the doped regions are electrically shorted, thereby varying the inductance of the inductor. In various embodiments, the inductor is electrically connected to a resistor and a capacitor to provide a tunable RLC circuit. Other aspects and embodiments are provided herein.

Abstract: Apparatus, methods, and systems for sorting nanostructures, such as nanodots or nanotubes, are described. Sorting the nanostructures removes remnants of the nanotube fabrication from a mixture or bundle of material. The sorting activity may include suspending the mixture in a plasma to separate nanostructures and remnant material. A motive force, such as gas flow or laser, can be applied to the suspended nanostructures and remnants to move larger material out of the plasma, leaving smaller material trapped in the plasma. Additional embodiments are disclosed.

Abstract: A voltage-controlled semiconductor inductor and method is provided. According to various embodiments, the voltage-controlled inductor includes a conductor configured with a number of inductive coils. The inductor also includes a semiconductor material having a contact with at least a portion of at least one of the coils. The semiconductor material is doped to form a diode with a first doped region of first conductivity type, a second doped region of second conductivity type, and a depletion region. A voltage across the diode changes lengths of the first doped region, the second doped region and the depletion region, and adjacent coils in contact with at least one of the doped regions are electrically shorted, thereby varying the inductance of the inductor. In various embodiments, the inductor is electrically connected to a resistor and a capacitor to provide a tunable RLC circuit. Other aspects and embodiments are provided herein.

Abstract: Methods and systems for sorting nanostructures, such as nanodot or nanotubes, are described. The sorting of the nanostructures removes remnants of the nanotube fabrication from the mixture or bundle of material. The sorting includes suspending the mixture in a plasma, which separated the nanostructures and remnant material. A motive force, such as gas flow or laser, is applied to the suspended nanostructures and remnants such that the larger material moves out of the plasma while the smaller material remains trapped in the plasma.

Abstract: A method of etching trenches into silicon of a semiconductor substrate includes forming a mask over silicon of a semiconductor substrate, with the mask comprising trenches formed there-through. Plasma etching is conducted to form trenches into the silicon of the semiconductor substrate using the mask. In one embodiment, the plasma etching includes forming an etching plasma using precursor gases which include SF6, an oxygen-containing compound, and a nitrogen-containing compound. In one embodiment, the plasma etching includes an etching plasma which includes a sulfur-containing component, an oxygen-containing component, and NFx.