Patents by Inventor Krupakar Murali Subramanian

Krupakar Murali Subramanian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180291605
    Abstract: Disclosure provides mechanical odor trap mechanism that can be coupled anywhere in the plumbing of a urinal system below the operative base. A receptacle is provided to receive and discharge the fluid from the urinal via a floatation device that is configured to float in the presence of fluid and settle down into the discharge opening in the absence of fluid to sealingly close the opening and block the escape of odor. A self cleaning urinal system can be configured to implement such mechanical odor trap mechanism and further be configured with spraying mechanism disposed at an elevation to spray water and/or air jets to wash away splattered fluid residue. A feces, urine and wash water separating toilet pan can be provided with a lid configured to sealingly close the opening for feces to enable washing without the user shifting positions and also to block odor.
    Type: Application
    Filed: April 21, 2016
    Publication date: October 11, 2018
    Inventor: Krupakar Murali Subramanian
  • Patent number: 9679781
    Abstract: Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.
    Type: Grant
    Filed: April 13, 2015
    Date of Patent: June 13, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Mirzafer Abatchev, David Wells, Baosuo Zhou, Krupakar Murali Subramanian
  • Publication number: 20150318149
    Abstract: Systems and methods for high pressure plasma discharge, wherein a system comprises at least one electrode which is fragmented into pieces and arranged to form a fragmented electrode system; at least one dielectric material placed between or parallel to the at least one electrode and another second electrode or fragmented pieces of the fragmented electrode systems, wherein the at least one electrode or fragmented pieces of the fragmented electrode system may have same or opposite charge; and at least one power supply unit; wherein the pieces of the electrode which is fragmented can be arranged parallel or divergent or convergent to one another and are at an angle to each other or the central axis passing through the electrode.
    Type: Application
    Filed: December 11, 2013
    Publication date: November 5, 2015
    Inventor: Krupakar Murali Subramanian
  • Publication number: 20150287610
    Abstract: Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.
    Type: Application
    Filed: April 13, 2015
    Publication date: October 8, 2015
    Inventors: MIRZAFER ABATCHEV, DAVID WELLS, BAOSUO ZHOU, KRUPAKAR MURALI SUBRAMANIAN
  • Patent number: 9003651
    Abstract: Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.
    Type: Grant
    Filed: July 5, 2013
    Date of Patent: April 14, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Mirzafer Abatchev, David Wells, Baosuo Zhou, Krupakar Murali Subramanian
  • Patent number: 8747557
    Abstract: The present invention is generally directed to a system for controlling placement of nanoparticles, and methods of using same. In one illustrative embodiment, the device includes a substrate and a plurality of funnels in the substrate, wherein each of the funnels comprises an inlet opening and an elongated, rectangular shaped outlet opening. In one illustrative embodiment, the method includes creating a dusty plasma comprising a plurality of carbon nanotubes, positioning a mask between the dusty plasma and a desired target for the carbon nanotubes, the mask having a plurality of openings extending therethrough, and extinguishing the dusty plasma to thereby allow at least some of the carbon nanotubes in the dusty plasma to pass through at least some of the plurality of openings in the mask and land on the target.
    Type: Grant
    Filed: March 5, 2009
    Date of Patent: June 10, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Krupakar Murali Subramanian, Neal Rueger, Gurtej Sandhu
  • Publication number: 20130295770
    Abstract: Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.
    Type: Application
    Filed: July 5, 2013
    Publication date: November 7, 2013
    Inventors: Mirzafer Abatchev, David Wells, Baosuo ` Zhou, Krupakar Murali Subramanian
  • Patent number: 7662718
    Abstract: Methods of etching substrates employing a trim process for critical dimension control for integrated circuits are disclosed. In one embodiment, the method of etching includes providing a first hard mask layer over a target layer; providing a second hard mask layer over the first hard mask layer; providing a photoresist layer over the second hard mask layer; forming a pattern in the photoresist layer; transferring the pattern into the second hard mask layer; and trimming the second hard mask layer with the photoresist layer on top of the second hard mask layer. The top surface of the second hard mask layer is protected by the photoresist and the substrate is protected by the overlying first hard mask layer during the trim etch, which can therefore be aggressive.
    Type: Grant
    Filed: March 9, 2006
    Date of Patent: February 16, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Mirzafer K. Abatchev, Krupakar Murali Subramanian, Baosuo Zhou
  • Publication number: 20090308312
    Abstract: The present invention is generally directed to a system for controlling placement of nanoparticles, and methods of using same. In one illustrative embodiment, the device includes a substrate and a plurality of funnels in the substrate, wherein each of the funnels comprises an inlet opening and an elongated, rectangular shaped outlet opening. In one illustrative embodiment, the method includes creating a dusty plasma comprising a plurality of carbon nanotubes, positioning a mask between the dusty plasma and a desired target for the carbon nanotubes, the mask having a plurality of openings extending therethrough, and extinguishing the dusty plasma to thereby allow at least some of the carbon nanotubes in the dusty plasma to pass through at least some of the plurality of openings in the mask and land on the target.
    Type: Application
    Filed: March 5, 2009
    Publication date: December 17, 2009
    Inventors: Krupakar Murali Subramanian, Neal Rueger, Gurtej Sandhu
  • Patent number: 7517558
    Abstract: The present invention is generally directed to a system for controlling placement of nanoparticles, and methods of using same. In one illustrative embodiment, the device includes a substrate and a plurality of funnels in the substrate, wherein each of the funnels comprises an inlet opening and an elongated, rectangular shaped outlet opening. In one illustrative embodiment, the method includes creating a dusty plasma comprising a plurality of carbon nanotubes, positioning a mask between the dusty plasma and a desired target for the carbon nanotubes, the mask having a plurality of openings extending therethrough, and extinguishing the dusty plasma to thereby allow at least some of the carbon nanotubes in the dusty plasma to pass through at least some of the plurality of openings in the mask and land on the target.
    Type: Grant
    Filed: June 6, 2005
    Date of Patent: April 14, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Krupakar Murali Subramanian, Neal Rueger, Gurtej Sandhu