Abstract: Methods of etching substrates employing a trim process for critical dimension control for integrated circuits are disclosed. In one embodiment, the method of etching includes providing a first hard mask layer over a target layer; providing a second hard mask layer over the first hard mask layer; providing a photoresist layer over the second hard mask layer; forming a pattern in the photoresist layer; transferring the pattern into the second hard mask layer; and trimming the second hard mask layer with the photoresist layer on top of the second hard mask layer. The top surface of the second hard mask layer is protected by the photoresist and the substrate is protected by the overlying first hard mask layer during the trim etch, which can therefore be aggressive.

Abstract: A method for reducing line edge roughness comprises forming a masking structure on a substrate assembly, wherein the substrate assembly includes a number of layers. The method includes forming a layered masking structure by depositing a layer of material on the masking structure in order to reduce a line edge roughness (LER) of the masking structure, and etching a pattern of the layered masking structure into one or more of the number of layers of the substrate assembly before trimming the layered masking structure.

Abstract: The present invention is generally directed to corona discharge plasma source devices, and various systems and methods for using same. In one illustrative embodiment, the system comprises a process chamber, a support member comprising a plurality of tapered conductive members positioned in the member and a power supply system for applying at least one voltage level to the plurality of tapered conductive members.

Abstract: A carbon or carbon-containing underlayer, which is used as a mask, is patterned using a process comprising, in one specific embodiment, boron trichloride and oxygen under specified processing conditions to etch the underlayer. The underlayer is then used as a mask to etch a layer below the underlayer, such as a semiconductor wafer or a layer formed as part of a semiconductor wafer substrate assembly. Various processing conditions are described, as is the formation of various features using embodiments of the inventive process.

Abstract: The invention includes methods of etching substrates, methods of forming features on substrates, and methods of depositing a layer comprising silicon, carbon and fluorine onto a semiconductor substrate. In one implementation, a method of etching includes forming a masking feature projecting from a substrate. The feature has a top, opposing sidewalls, and a base. A layer comprising SixCyFz is deposited over the feature, where “x” is from 0 to 0.2, “y” is from 0.3 to 0.9, and “z” is from 0.1 to 0.6. The SixCyFz—comprising layer and upper portions of the feature opposing sidewalls are etched effective to laterally recess such upper portions proximate the feature top relative to lower portions of the feature opposing sidewalls proximate the feature base. After such etching of the SixCyFz—comprising layer and such etching of upper portions of the feature sidewalls, the substrate is etched using the masking feature as a mask.

Abstract: Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.

Abstract: Methods and systems for sorting nanostructures, such as nanodot or nanotubes, are described. The sorting of the nanostructures removes remnants of the nanotube fabrication from the mixture or bundle of material. The sorting includes suspending the mixture in a plasma, which separated the nanostructures and remnant material. A motive force, such as gas flow or laser, is applied to the suspended nanostructures and remnants such that the larger material moves out of the plasma while the smaller material remains trapped in the plasma.

Abstract: A voltage-controlled semiconductor inductor and method is provided. According to various embodiments, the voltage-controlled inductor includes a conductor configured with a number of inductive coils. The inductor also includes a semiconductor material having a contact with at least a portion of at least one of the coils. The semiconductor material is doped to form a diode with a first doped region of first conductivity type, a second doped region of second conductivity type, and a depletion region. A voltage across the diode changes lengths of the first doped region, the second doped region and the depletion region, and adjacent coils in contact with at least one of the doped regions are electrically shorted, thereby varying the inductance of the inductor. In various embodiments, the inductor is electrically connected to a resistor and a capacitor to provide a tunable RLC circuit. Other aspects and embodiments are provided herein.

Abstract: A method for forming a template useful for nanoimprint lithography comprises forming at least one pillar which provides a topographic feature extending from a template base. At least one conformal pattern layer and one conformal spacing layer, and generally a plurality of alternating pattern layers and spacing layers, are formed over the template base and pillar. A planarized filler layer is formed over the pattern and spacing layers, then the filler, the spacing layer and the pattern layer are partially removed, for example using mechanical polishing, to expose the pillar. One or more etches are performed to remove at least a portion of the pillar, the filler, and the spacing layer to result in the pattern layer protruding from the spacing layer and providing the template pattern.

Abstract: The invention includes methods of etching substrates, methods of forming features on substrates, and methods of depositing a layer comprising silicon, carbon and fluorine onto a semiconductor substrate. In one implementation, a method of etching includes forming a masking feature projecting from a substrate. The feature has a top, opposing sidewalls, and a base. A layer comprising SixCyFz is deposited over the feature, where “x” is from 0 to 0.2, “y” is from 0.3 to 0.9, and “z” is from 0.1 to 0.6. The SixCyFz-comprising layer and upper portions of the feature opposing sidewalls are etched effective to laterally recess such upper portions proximate the feature top relative to lower portions of the feature opposing sidewalls proximate the feature base. After such etching of the SixCyFz-comprising layer and such etching of upper portions of the feature sidewalls, the substrate is etched using the masking feature as a mask.

Abstract: The invention includes a template comprising one or both of CdS and CdSe adhered to a base in a desired pattern. The base can be any transparent or translucent material, and the desired pattern can include two or more separated segments. The template can be utilized for patterning a plurality of substrates. For instance, the substrates can be provided to have masking layers thereover, and the CdS and/or CdSe can be utilized as catalytic material to sequentially impart patterns in the masking layers. The imparting of the patterns can modify some regions of the masking layers relative to others, and either the modified or unmodified regions can be selectively removed to form patterned masks from the masking layers. Patterns from the patterned masks can then be transferred into the substrates.

Abstract: The present invention is generally directed to a system for controlling placement of nanoparticles, and methods of using same. In one illustrative embodiment, the device includes a substrate and a plurality of funnels in the substrate, wherein each of the funnels comprises an inlet opening and an elongated, rectangular shaped outlet opening. In one illustrative embodiment, the method includes creating a dusty plasma comprising a plurality of carbon nanotubes, positioning a mask between the dusty plasma and a desired target for the carbon nanotubes, the mask having a plurality of openings extending therethrough, and extinguishing the dusty plasma to thereby allow at least some of the carbon nanotubes in the dusty plasma to pass through at least some of the plurality of openings in the mask and land on the target.

Abstract: Ion Implantation into surfaces of three-dimensional metallic and non-metallic targets is achieved by building a metallic mesh enclosure around the target through rapid-prototyping and then forming an ionized plasma about the target within an enclosing chamber and applying a pulse of high voltage between the wire mesh and the conductive walls of the chamber. The ions from the plasma are driven towards the wire mesh, since the mesh has finite transparency; some of the ions continue to move towards the target and are driven into the target from all sides simultaneously without the need of manipulation of the target object. Repetitive and alternating pulses of high voltages, typically 1 kV or higher, causes the ions to be implanted into the surface of the target. The plasma may be formed of a neutral gas introduced into the evacuated chamber and ionized therein with ionizing radiation so that a constant source of plasma is provided which surrounds the target object during the implantation process.

Abstract: A method for changing the chemical properties of fluid media is carried out in a coaxial plasma reactor. The plasma reaction in the reactor produces reactive species, such as electrons, ions and free radicals that promote better flammability of the combustible liquids, helps isolates unwanted pollutants such as sulfur and nitrogen by forming heavier compounds and also helps inactivate any microorganisms in other fluids such as water. In various embodiments, the plasma reaction also sputters off minute particles from the interior surfaces of plasma reactor. Such nanoparticles helps lower the combustion temperature of the flammable fluids and disinfect other fluids such as water. In another embodiment, breaking the bubbles into smaller size using an ultrasound generator increases the efficiency of the plasma reactor. In another embodiment, the bubbles are broken into smaller size and mixed with the fluid by agitating the liquid using a mechanical stirrer.