Patents by Inventor Krupal Jitendra Mehta

Krupal Jitendra Mehta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11906585
    Abstract: Built-in-self-test (BIST operations are performed by receiver lanes of a multilane receiver system, wherein at least one receiver lane is configured as a synthesized clock source for other receiver lanes configured to perform BIST operations. The at least one receiver lane configured as the synthesized clock source may generate a clock signal and provide the clock signal to the other receiver lanes performing the BIST operations. In some examples, digital control signals may be used for coordinating the enablement of the at least one receiver lane to function as the synthesized clock source and for coordinating the enablement of the other receiver lanes to perform BIST operations.
    Type: Grant
    Filed: April 1, 2022
    Date of Patent: February 20, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: A Santosh Kumar Reddy, Gunjan Mandal, Parin Rajnikant Bhuta, Raghavendra Molthati, Saikat Hazra, Sanjeeb Kumar Ghosh, Sunil Rajan, Krupal Jitendra Mehta, Praveen S Bharadwaj
  • Publication number: 20230194608
    Abstract: The present disclosure provides systems and methods for performing built-in-self-test (BIST) operations without a dedicated clock source. The BIST operations are performed by receiver lanes of a multilane receiver system, wherein at least one receiver lane is configured as synthesized clock source for other receiver lanes configured to perform BIST operations. The at least one receiver lane configured as the synthesized clock source may generate a clock signal and provide the clock signal to the other receiver lanes performing the BIST operations. In some examples, digital control signals may be used for coordinating the enablement of the at least one receiver lane to function as the synthesized clock source and for coordinating the enablement of the other receiver lanes to perform BIST operations.
    Type: Application
    Filed: April 1, 2022
    Publication date: June 22, 2023
    Inventors: A Santosh Kumar Reddy, Gunjan Mandal, Parin Rajnikant Bhuta, Raghavendra Molthati, Saikat Hazra, Sanjeeb Kumar Ghosh, Sunil Rajan, Krupal Jitendra Mehta, Praveen S. Bharadwaj