Abstract: Low-power, easily scalable architectures for high-speed data handling are critical to modern circuits and systems. Successful architectures must provide efficient data storage and efficient/flexible data retrieval with low power consumption. Data encoding, including that achieved with turbo codes, have data streams split into a sequence of even and odd data bits. These bits are written into multiple single-port memories so that the writing alternates between memories. Scheduling for the reading and writing is performed to avoid conflicts and give priority to the read operations.

Abstract: A method and system for low-complexity implementation of a Viterbi Decoder with near optimal performance has been disclosed. The Viterbi decoding technique is diagrammatically represented as a trellis. The trellis includes various states at different time instants, and branches connecting these states. Each state has an associated state metric and a survivor path sequence, whereas each branch has a branch metric. The state metric for each current state is checked for crossing a predefined limit. If it crosses the predefined limit, the state metric is updated with a new metric that is obtained by subtracting a constant value from the state metric. Thereafter, the method finds a common path in the trellis at each state and updates the survivor path sequence of each state. The Most Significant Bits (MSBs) of the survivor path sequences of the states at a particular time instant are computed and the original data is decoded, based on the count of ‘0s’ and ‘1s’ in the MSBs.