Patents by Inventor Krystyna W. Semkow

Krystyna W. Semkow has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multilayer pillar for reduced stress interconnect and method of making same
    Patent number: 11244917
    Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: February 8, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Virendra R. Jadhav, Krystyna W. Semkow, Kamalesh K. Srivastava, Brian R. Sundlof
  • Multilayer pillar for reduced stress interconnect and method of making same
    Patent number: 11171102
    Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: November 9, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Virendra R. Jadhav, Krystyna W. Semkow, Kamalesh K. Srivastava, Brian R. Sundlof
  • Multilayer pillar for reduced stress interconnect and method of making same
    Patent number: 11094657
    Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: August 17, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Virendra R. Jadhav, Krystyna W. Semkow, Kamalesh K. Srivastava, Brian R. Sundlof
  • MULTILAYER PILLAR FOR REDUCED STRESS INTERCONNECT AND METHOD OF MAKING SAME
    Publication number: 20190326243
    Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate.
    Type: Application
    Filed: July 3, 2019
    Publication date: October 24, 2019
    Inventors: Virendra R. JADHAV, Krystyna W. SEMKOW, Kamalesh K. SRIVASTAVA, Brian R. SUNDLOF
  • MULTILAYER PILLAR FOR REDUCED STRESS INTERCONNECT AND METHOD OF MAKING SAME
    Publication number: 20190326242
    Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate.
    Type: Application
    Filed: July 3, 2019
    Publication date: October 24, 2019
    Inventors: Virendra R. JADHAV, Krystyna W. SEMKOW, Kamalesh K. SRIVASTAVA, Brian R. SUNDLOF
  • Multilayer pillar for reduced stress interconnect and method of making same
    Patent number: 10403590
    Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: September 3, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Virendra R. Jadhav, Krystyna W. Semkow, Kamalesh K. Srivastava, Brian R. Sundlof
  • Multilayer pillar for reduced stress interconnect and method of making same
    Patent number: 10396051
    Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: August 27, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Virendra R. Jadhav, Krystyna W. Semkow, Kamalesh K. Srivastava, Brian R. Sundlof
  • MULTILAYER PILLAR FOR REDUCED STRESS INTERCONNECT AND METHOD OF MAKING SAME
    Publication number: 20190157230
    Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate.
    Type: Application
    Filed: January 17, 2019
    Publication date: May 23, 2019
    Inventors: Virendra R. JADHAV, Krystyna W. SEMKOW, Kamalesh K. SRIVASTAVA, Brian R. SUNDLOF
  • MULTILAYER PILLAR FOR REDUCED STRESS INTERCONNECT AND METHOD OF MAKING SAME
    Publication number: 20170170135
    Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate.
    Type: Application
    Filed: February 28, 2017
    Publication date: June 15, 2017
    Inventors: Virendra R. JADHAV, Krystyna W. SEMKOW, Kamalesh K. SRIVASTAVA, Brian R. SUNDLOF
  • MULTILAYER PILLAR FOR REDUCED STRESS INTERCONNECT AND METHOD OF MAKING SAME
    Publication number: 20170133338
    Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate.
    Type: Application
    Filed: January 13, 2017
    Publication date: May 11, 2017
    Inventors: Virendra R. JADHAV, Krystyna W. SEMKOW, Kamalesh K. SRIVASTAVA, Brian R. SUNDLOF
  • Multilayer pillar for reduced stress interconnect and method of making same
    Patent number: 9640501
    Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: May 2, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Virendra R. Jadhav, Krystyna W. Semkow, Kamalesh K. Srivastava, Brian R. Sundlof
  • Multilayer pillar for reduced stress interconnect and method of making same
    Patent number: 9472520
    Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: October 18, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Virendra R. Jadhav, Krystyna W. Semkow, Kamalesh K. Srivastava, Brian R. Sundlof
  • Electromigration-resistant lead-free solder interconnect structures
    Patent number: 9379007
    Abstract: Embodiments of the invention include a lead-free solder interconnect structure and methods for making a lead-free interconnect structure. The structure includes a semiconductor substrate having a last metal layer, a copper pedestal attached to the last metal layer, a barrier layer attached to the copper pedestal, a barrier protection layer attached to the barrier layer, and a lead-free solder layer contacting at least one side of the copper pedestal.
    Type: Grant
    Filed: May 1, 2013
    Date of Patent: June 28, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Charles L. Arvin, Kenneth Bird, Charles C. Goldsmith, Sung K. Kang, Minhua Lu, Clare J. McCarthy, Eric D. Perfecto, Srinivasa S. N. Reddy, Krystyna W. Semkow, Thomas A. Wassick
  • Multilayer pillar for reduced stress interconnect and method of making same
    Patent number: 9111816
    Abstract: A multi-layer pillar is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions.
    Type: Grant
    Filed: March 27, 2012
    Date of Patent: August 18, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Virendra R. Jadhav, Krystyna W. Semkow, Kamalesh K. Srivastava, Brian R. Sundlof
  • Under ball metallurgy (UBM) for improved electromigration
    Patent number: 9084378
    Abstract: An interconnect structure that includes a substrate having an electrical component present therein, and a under-bump metallurgy (UBM) stack that is present in contact with a contact pad to the electrical component that is present in the substrate. The UBM stack includes a metallic adhesion layer that is direct contact with the contact pad to the electrical component, a copper (Cu) seed layer that is in direct contact with the metallic adhesion layer, a first nickel (Ni) barrier layer that is present in direct contact with copper (Cu) seed layer, and a layered structure of at least one copper (Cu) conductor layer and at least one second nickel (Ni) barrier layer present on the first nickel (Ni) barrier layer. A solder ball may be present on second nickel (Ni) barrier layer.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: July 14, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Charles L. Arvin, Minhua Lu, Eric D. Perfecto, Krystyna W. Semkow, Thomas A. Wassick
  • Structures for improving current carrying capability of interconnects and methods of fabricating the same
    Patent number: 9035459
    Abstract: Interconnect structures and methods of fabricating the same are provided. The interconnect structures provide highly reliable copper interconnect structures for improving current carrying capabilities (e.g., current spreading). The structure includes an under bump metallurgy formed in a trench. The under bump metallurgy includes at least: an adhesion layer; a plated barrier layer; and a plated conductive metal layer provided between the adhesion layer and the plated barrier layer. The structure further includes a solder bump formed on the under bump metallurgy.
    Type: Grant
    Filed: April 10, 2009
    Date of Patent: May 19, 2015
    Assignee: International Business Machines Corporation
    Inventors: Charles L. Arvin, Raschid J. Bezama, Harry D. Cox, Timothy H. Daubenspeck, Krystyna W. Semkow, Timothy D. Sullivan
  • MULTILAYER PILLAR FOR REDUCED STRESS INTERCONNECT AND METHOD OF MAKING SAME
    Publication number: 20150054152
    Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate.
    Type: Application
    Filed: October 29, 2014
    Publication date: February 26, 2015
    Inventors: Virendra R. JADHAV, Krystyna W. SEMKOW, Kamalesh K. SRIVASTAVA, Brian R. SUNDLOF
  • Semiconductor device having a copper plug
    Patent number: 8922019
    Abstract: Disclosed is a semiconductor device wherein an insulation layer has a via opening with an aluminum layer in the via opening and in contact with the last wiring layer of the device. There is a barrier layer on the aluminum layer followed by a copper plug which fills the via opening. Also disclosed is a process for making the semiconductor device.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: December 30, 2014
    Assignee: International Business Machines Corporation
    Inventors: Mukta G. Farooq, Emily R. Kinser, Ian D. Melville, Krystyna W. Semkow
  • Additives for grain fragmentation in Pb-free Sn-based solder
    Patent number: 8910853
    Abstract: In one embodiment of the present invention, inert nano-sized particles having dimensions from 1 nm to 1,000 nm are added into a solder ball. The inert nano-sized particles may comprise metal oxides, metal nitrides, metal carbides, metal borides, etc. The inert nano-sized particles may be a single compound, or may be a metallic material having a coating of a different material. In another embodiment of the present invention, a small quantity of at least one elemental metal that forms stable high melting intermetallic compound with tin is added to a solder ball. The added at least one elemental metal forms precipitates of intermetallic compounds with tin, which are dispersed as fine particles in the solder.
    Type: Grant
    Filed: July 1, 2013
    Date of Patent: December 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Charles L. Arvin, Alexandre Blander, Peter J. Brofman, Donald W. Henderson, Gareth G. Hougham, Hsichang Liu, Eric D. Perfecto, Srinivasa S.N. Reddy, Krystyna W. Semkow, Kamalesh K. Srivastava, Brian R. Sundlof, Julien Sylvestre, Renee L. Weisman
  • UNDER BALL METALLURGY (UBM) FOR IMPROVED ELECTROMIGRATION
    Publication number: 20140339699
    Abstract: An interconnect structure that includes a substrate having an electrical component present therein, and a under-bump metallurgy (UBM) stack that is present in contact with a contact pad to the electrical component that is present in the substrate. The UBM stack includes a metallic adhesion layer that is direct contact with the contact pad to the electrical component, a copper (Cu) seed layer that is in direct contact with the metallic adhesion layer layer, a first nickel (Ni) barrier layer that is present in direct contact with copper (Cu) seed layer, and a layered structure of at least one copper (Cu) conductor layer and at least one second nickel (Ni) barrier layer present on the first nickel (Ni) barrier layer. A solder ball may be present on second nickel (Ni) barrier layer.
    Type: Application
    Filed: July 31, 2014
    Publication date: November 20, 2014
    Applicant: International Business Machines Corporation
    Inventors: Charles L. Arvin, Minhua Lu, Eric D. Perfecto, David J. Russell, Wolfgang Sauter, Krystyna W. Semkow, Thomas A. Wassick