Patents by Inventor Ksenija Lakovic
Ksenija Lakovic has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8423873Abstract: Two levels of error correction decoding are performed using first and second level decoders. A composite code formed by combining an inner component code and an outer component code can be used to decode the data and correct any errors. Performing two level decoding using a composite code allows the size of the inner parity block to be reduced to a single Reed-Solomon symbol while keeping a good code rate. The first level decoder generates soft information. The soft information can indicate a most likely error event for each possible syndrome value of the inner component code. The soft information can also include error metric values for each of the most likely error events. The second level decoder generates corrected syndrome values based on the soft information using the outer component code. The most likely trellis path that corresponds to the corrected syndrome values is then selected.Type: GrantFiled: May 25, 2010Date of Patent: April 16, 2013Assignee: HGST Netherlands B.V.Inventors: Shaohua Yang, Richard Leo Galbraith, Ksenija Lakovic, Yuan Xing Lee, Travis Oenning, Jongseung Park, Hideki Sawaguchi, Bruce A. Wilson
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Patent number: 8209578Abstract: A system corrects errors in a bit stream. The system includes an encoder and a decoder. The encoder encodes the bit stream using a low density parity check code by inserting parity check bits into the bit stream to generate codewords. The decoder decodes the codewords using parity check equations that are based on the low density parity check code. The parity check bits may comprise no more than four percent of the bits in the codewords of the low density parity check code. The low density parity check code can have a minimum separation of at least 7 between any two ones in each row of a parity-check matrix that is based on the low density parity check code. The encoder and the decoder can be defined in hardware using logic circuits that are interconnected to implement a trellis based on the low density parity check code.Type: GrantFiled: March 11, 2008Date of Patent: June 26, 2012Assignee: Hitachi Global Storage Technologies Netherlands, B.V.Inventors: Richard Leo Galbraith, Bruce Alexander Wilson, Travis Roger Oenning, Mario Blaum, Ksenija Lakovic, Ivana Djurdjevic
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Patent number: 8189282Abstract: Servo patterns for patterned media. The servo pattern includes specification of cylinder/track ID with and without a Gray code. The servo pattern space is minimized by the optimum usage of the islands. This is achieved by island allocation rules to take advantage of non-magnetic island. The island allocation also provides for easier lift-off. Logic is used to encode and decode the Gray code. Further, the Gray code is designed to stabilize the magnetic island/non-magnetic island ratio to allow for easier manufacture.Type: GrantFiled: March 15, 2010Date of Patent: May 29, 2012Assignee: Hitachi Global Storage Technologies Netherlands B.V.Inventors: Thomas Robert Albrecht, Mario Blaum, Ksenija Lakovic, Bruce Alexander Wilson, Satoshi Yamamoto
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Patent number: 8037393Abstract: A detector generates a detected sequence, and a post processor generates probability values that indicate the likelihood of a plurality of error events in the detected sequence. The post processor partitions the values into first and second subsets. The post processor selects a first most likely value from the first subset of the values and a second most likely value from the second subset of the values. The post processor generates a bit reliability based on the first and the second most likely values.Type: GrantFiled: June 29, 2007Date of Patent: October 11, 2011Assignee: Hitachi Global Storage Technologies Netherlands, B.V.Inventors: Ivana Djurdjevic, Richard Leo Galbraith, Bruce Alexander Wilson, Yuan Xing Lee, Travis Roger Oenning, Mario Blaum, Ksenija Lakovic, Zongwang Li
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Patent number: 8037394Abstract: Techniques are provided that generate bit reliabilities for a detected sequence. A detector generates the detected sequence. According to one embodiment, a post-processor finds a first set of combinations of one or more error events in the detected sequence satisfying a complete set or a subset of error correction constraints corresponding to the first bit value, finds a second set of combinations of one or more error events in the detected sequence satisfying a complete set or a subset of error correction constraints corresponding to the second bit value, selects a first most likely combination of one or more events of the first set and a second most likely combination of one or more events of the second set, and generates a bit reliability based on the first and the second most likely values.Type: GrantFiled: June 29, 2007Date of Patent: October 11, 2011Assignee: Hitachi Global Storage Technologies Netherlands, B.V.Inventors: Ivana Djurdjevic, Bruce Alexander Wilson, Mario Blaum, Richard Leo Galbraith, Ksenija Lakovic, Yuan Xing Lee, Zongwang Li, Travis Roger Oenning
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Publication number: 20100235718Abstract: Two levels of error correction decoding are performed using first and second level decoders. A composite code formed by combining an inner component code and an outer component code can be used to decode the data and correct any errors. Performing two level decoding using a composite code allows the size of the inner parity block to be reduced to a single Reed-Solomon symbol while keeping a good code rate. The first level decoder generates soft information. The soft information can indicate a most likely error event for each possible syndrome value of the inner component code. The soft information can also include error metric values for each of the most likely error events. The second level decoder generates corrected syndrome values based on the soft information using the outer component code. The most likely trellis path that corresponds to the corrected syndrome values is then selected.Type: ApplicationFiled: May 25, 2010Publication date: September 16, 2010Applicant: Hitachi Global Storage Technologies Netherlands, B.V.Inventors: Shaohua Yang, Richard Leo Galbraith, Ksenija Lakovic, Yuan Xing Lee, Travis Oenning, Jongseung Park, Hideki Sawaguchi, Bruce A. Wilson
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Publication number: 20100172048Abstract: Servo patterns for patterned media. The servo pattern includes specification of cylinder/track ID with and without a Gray code. The servo pattern space is minimized by the optimum usage of the islands. This is achieved by island allocation rules to take advantage of non-magnetic island. The island allocation also provides for easier lift-off. Logic is used to encode and decode the Gray code. Further, the Gray code is designed to stabilize the magnetic island/non-magnetic island ratio to allow for easier manufacture.Type: ApplicationFiled: March 15, 2010Publication date: July 8, 2010Inventors: Thomas Robert Albrecht, Mario Blaum, Ksenija Lakovic, Bruce Alexander Wilson, Satoshi Yamamoto
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Patent number: 7725800Abstract: Two levels of error correction decoding are performed using first and second level decoders. A composite code formed by combining an inner component code and an outer component code can be used to decode the data and correct any errors. Performing two level decoding using a composite code allows the size of the inner parity block to be reduced to a single Reed-Solomon symbol while keeping a good code rate. The first level decoder generates soft information. The soft information can indicate a most likely error event for each possible syndrome value of the inner component code. The soft information can also include error metric values for each of the most likely error events. The second level decoder generates corrected syndrome values based on the soft information using the outer component code. The most likely trellis path that corresponds to the corrected syndrome values is then selected.Type: GrantFiled: August 5, 2005Date of Patent: May 25, 2010Assignee: Hitachi Global Stroage Technologies Netherlands, B.V.Inventors: Shaohua Yang, Richard Leo Galbraith, Ksenija Lakovic, Yuan Xing Lee, Travis Oenning, Jongseung Park, Hideki Sawaguchi, Bruce A. Wilson
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Patent number: 7715137Abstract: Servo patterns for patterned media. The servo pattern includes specification of cylinder/track ID with and without a Gray code. The servo pattern space is minimized by the optimum usage of the islands. This is achieved by island allocation rules to take advantage of non-magnetic island. The island allocation also provides for easier lift-off. Logic is used to encode and decode the Gray code. Further, the Gray code is designed to stabilize the magnetic island/non-magnetic island ratio to allow for easier manufacture.Type: GrantFiled: October 19, 2006Date of Patent: May 11, 2010Assignee: Hitachi Global Storage Technologies Netherlands B.V.Inventors: Thomas Robert Albrecht, Mario Blaum, Ksenija Lakovic, Bruce Alexander Wilson, Satoshi Yamamoto
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Patent number: 7696908Abstract: Techniques are provided for reducing error propagation in encoded data using Fibonacci modulation codes. The Fibonacci modulation codes have a Fibonacci base with a variable span that limits error propagation. Some of the elements in the Fibonacci base have a larger span than limited span elements in the base. Errors occurring in bit positions of an encoded sequence that correspond to the limited span elements do not propagate to adjacent bytes in the decoded sequence. The Fibonacci modulation codes can also have a relatively high code rate.Type: GrantFiled: January 4, 2006Date of Patent: April 13, 2010Assignee: Hitachi Global Storage Technologies Netherlands, B.V.Inventors: Mario Blaum, Ksenija Lakovic
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Publication number: 20090235142Abstract: A system corrects errors in a bit stream. The system includes an encoder and a decoder. The encoder encodes the bit stream using a low density parity check code by inserting parity check bits into the bit stream to generate codewords. The decoder decodes the codewords using parity check equations that are based on the low density parity check code. The parity check bits may comprise no more than four percent of the bits in the codewords of the low density parity check code. The low density parity check code can have a minimum separation of at least 7 between any two ones in each row of a parity-check matrix that is based on the low density parity check code. The encoder and the decoder can be defined in hardware using logic circuits that are interconnected to implement a trellis based on the low density parity check code.Type: ApplicationFiled: March 11, 2008Publication date: September 17, 2009Applicant: Hitachi Global Storage Technologies Netherlands, B.V.Inventors: Richard Leo Galbraith, Bruce Alexander Wilson, Travis Roger Oenning, Mario Blaum, Ksenija Lakovic, Ivana Djurdjevic
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Patent number: 7590920Abstract: An error correction encoder inserts redundant parity information into a data stream to improve system reliability. The encoder can generate the redundant parity information using a composite code. Dummy bits are inserted into the data stream in locations reserved for parity information generated by subsequent encoding. The error correction code can have a uniform or a non-uniform span. The span corresponds to consecutive channel bits that are within a single block of a smaller parity code that is used to form a composite code. The span lengths can be variant across the whole codeword by inserting dummy bits in less than all of the spans.Type: GrantFiled: August 5, 2005Date of Patent: September 15, 2009Assignee: Hitachi Global Storage Technologies Netherlands, B.V.Inventors: Shaohua Yang, Mario Blaum, Richard Leo Galbraith, Ksenija Lakovic, Yuan Xing Lee, Travis Oenning, Jongseung Park, Hideki Sawaguchi
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Publication number: 20090006930Abstract: A detector generates a detected sequence, and a post processor generates probability values that indicate the likelihood of a plurality of error events in the detected sequence. The post processor partitions the values into first and second subsets. The post processor selects a first most likely value from the first subset of the values and a second most likely value from the second subset of the values. The post processor generates a bit reliability based on the first and the second most likely values.Type: ApplicationFiled: June 29, 2007Publication date: January 1, 2009Applicant: Hitachi Global Storage Technologies Netherlands, B.V.Inventors: Ivana Djurdjevic, Richard Leo Galbraith, Bruce Alexander Wilson, Yuan Xing Lee, Travis Roger Oenning, Mario Blaum, Ksenija Lakovic, Zongwang Li
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Publication number: 20090006931Abstract: Techniques are provided that generate bit reliabilities for a detected sequence. A detector generates the detected sequence. According to one embodiment, a post-processor finds a first set of combinations of one or more error events in the detected sequence satisfying a complete set or a subset of error correction constraints corresponding to the first bit value, finds a second set of combinations of one or more error events in the detected sequence satisfying a complete set or a subset of error correction constraints corresponding to the second bit value, selects a first most likely combination of one or more events of the first set and a second most likely combination of one or more events of the second set, and generates a bit reliability based on the first and the second most likely values.Type: ApplicationFiled: June 29, 2007Publication date: January 1, 2009Applicant: Hitachi Global Storage Technologies Netherlands, B.V.Inventors: Ivana Djurdjevic, Bruce Alexander Wilson, Mario Blaum, Richard Leo Galbraith, Ksenija Lakovic, Yuan Xing Lee, Zongwang Li, Travis Roger Oenning
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Publication number: 20080094742Abstract: Servo patterns for patterned media. The servo pattern includes specification of cylinder/track ID with and without a Gray code. The servo pattern space is minimized by the optimum usage of the islands. This is achieved by island allocation rules to take advantage of non-magnetic island. The island allocation also provides for easier lift-off. Logic is used to encode and decode the Gray code. Further, the Gray code is designed to stabilize the magnetic island/non-magnetic island ratio to allow for easier manufacture.Type: ApplicationFiled: October 19, 2006Publication date: April 24, 2008Inventors: Thomas Robert Albrecht, Mario Blaum, Ksenija Lakovic, Bruce Alexander Wilson, Satoshi Yamamoto
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Publication number: 20070157067Abstract: Techniques are provided for reducing error propagation in encoded data using Fibonacci modulation codes. The Fibonacci modulation codes have a Fibonacci base with a variable span that limits error propagation. Some of the elements in the Fibonacci base have a larger span than limited span elements in the base. Errors occurring in bit positions of an encoded sequence that correspond to the limited span elements do not propagate to adjacent bytes in the decoded sequence. The Fibonacci modulation codes can also have a relatively high code rate.Type: ApplicationFiled: January 4, 2006Publication date: July 5, 2007Applicant: Hitachi Global Technologies Netherlands, B.V.Inventors: Mario Blaum, Ksenija Lakovic
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Publication number: 20070043997Abstract: An error correction encoder inserts redundant parity information into a data stream to improve system reliability. The encoder can generate the redundant parity information using a composite code. Dummy bits are inserted into the data stream in locations reserved for parity information generated by subsequent encoding. The error correction code can have a uniform or a non-uniform span. The span corresponds to consecutive channel bits that are within a single block of a smaller parity code that is used to form a composite code. The span lengths can be variant across the whole codeword by inserting dummy bits in less than all of the spans.Type: ApplicationFiled: August 5, 2005Publication date: February 22, 2007Applicant: Hitachi Global Technologies Netherlands, B.V.Inventors: Shaohua Yang, Mario Blaum, Richard Galbraith, Ksenija Lakovic, Yuan Lee, Travis Oenning, Jongseung Park, Hideki Sawaguchi
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Publication number: 20070044006Abstract: Two levels of error correction decoding are performed using first and second level decoders. A composite code formed by combining an inner component code and an outer component code can be used to decode the data and correct any errors. Performing two level decoding using a composite code allows the size of the inner parity block to be reduced to a single Reed-Solomon symbol while keeping a good code rate. The first level decoder generates soft information. The soft information can indicate a most likely error event for each possible syndrome value of the inner component code. The soft information can also include error metric values for each of the most likely error events. The second level decoder generates corrected syndrome values based on the soft information using the outer component code. The most likely trellis path that corresponds to the corrected syndrome values is then selected.Type: ApplicationFiled: August 5, 2005Publication date: February 22, 2007Applicant: Hitachi Global Technologies Netherlands, B.V.Inventors: Shaohua Yang, Richard Galbraith, Ksenija Lakovic, Yuan Lee, Travis Oenning, Jongseung Park, Hideki Sawaguchi, Bruce Wilson
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Patent number: 7142134Abstract: Techniques are provided for performing substitutions of bit sequences that are known to cause errors. Input data is initially modulation encoded. The modulated data is then analyzed in a sliding window to determine if it contains any additional bit sequences that are known to cause errors. If an error prone bit sequence is identified in the data, a substitution engine replaces the error prone bit sequence with a predetermined pattern of bits that is less likely to cause errors. The bit stream output of the substitution engine is then recorded on a storage medium. The recorded bit stream is decoded when it read from the medium. The decoding process identifies the substituted bit pattern and replaces the substituted pattern with the original sequence of bits.Type: GrantFiled: February 1, 2005Date of Patent: November 28, 2006Assignee: Hitachi Global Storage Technologies Netherlands B.V.Inventors: Mario Blaum, Ksenija Lakovic, Bruce A. Wilson
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Patent number: 7126502Abstract: Techniques are provided for applying modulation constraints to data streams divided into separate interleaved portions. The even and odd bits in a data stream are separated into two data paths. A first modulation encoder encodes the even bits according to a first constraint. A second modulation encoder encodes the odd bits according to a second constraint. The two encoded data streams are then interleaved to form one data stream. The modulation encoders can encode the two data paths using Fibonacci encoding.Type: GrantFiled: February 1, 2005Date of Patent: October 24, 2006Assignee: Hitachi Global Storage Technologies Netherlands B.V.Inventors: Mario Blaum, Ksenija Lakovic, Bruce A. Wilson