Patents by Inventor Kshitij A. Doshi

Kshitij A. Doshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11171983
    Abstract: Embodiments are directed toward techniques to detect a first function associated with an address space initiating a call instruction to a second function in the address space, the first function to call the second function in a deprivileged mode of operation, and define accessible address ranges for segments of the address space for the second function, each segment to a have a different address range in the address space where the second function is permitted to access in the deprivileged mode of operation, Embodiments include switching to the stack associated with the second address space and the second function, and initiating execution of the second function in the deprivileged mode of operation.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: November 9, 2021
    Assignee: INTEL CORPORATION
    Inventors: Vadim Sukhomlinov, Kshitij Doshi, Michael Lemay, Dmitry Babokin, Areg Melik-Adamyan
  • Patent number: 11164083
    Abstract: Examples include techniques to manage training or trained models for deep learning applications. Examples include routing commands to configure a training model to be implemented by a training module or configure a trained model to be implemented by an inference module. The commands routed via out-of-band (OOB) link while training data for the training models or input data for the trained models are routed via inband links.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: November 2, 2021
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Suraj Prabhakaran, Kshitij A. Doshi, Da-Ming Chiang
  • Patent number: 11157422
    Abstract: In an example, there is disclosed a host-fabric interface (HFI), including: an interconnect interface to communicatively couple the HFI to an interconnect; a network interface to communicatively couple the HFI to a network; network interface logic to provide communication between the interconnect and the network; a coprocessor configured to provide an offloaded function for the network; a memory; and a caching agent configured to: designate a region of the memory as a shared memory between the HFI and a core communicatively coupled to the HFI via the interconnect; receive a memory operation directed to the shared memory; and issue a memory instruction to the memory according to the memory operation.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: October 26, 2021
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Daniel Rivas Barragan, Kshitij A. Doshi, Mark A. Schmisseur
  • Patent number: 11157642
    Abstract: An embodiment of a semiconductor apparatus may include technology to receive data with a unique identifier, and bypass encryption logic of a media controller based on the unique identifier. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: October 26, 2021
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Mark Schmisseur, Kshitij Doshi, Kapil Sood, Tarun Viswanathan
  • Publication number: 20210328886
    Abstract: Example methods, apparatus, and systems to facilitate service proxying are disclosed. An example apparatus includes interface circuitry to access a service request intercepted by from an infrastructure processing unit, the service request corresponding to a first node; instructions in the apparatus; and infrastructure sidecar circuitry to execute the instructions to: identify an active service instance corresponding to the service request; compare first telemetry data corresponding to the active service instance to a service quality metric; select a second node to service the service request based on the comparison and further telemetry data; and cause transmission of the service request to the second node.
    Type: Application
    Filed: June 25, 2021
    Publication date: October 21, 2021
    Inventors: Francesc Guim Bernat, Karthik Kumar, Kshitij Doshi, Marcos Carranza, Thijs Metsch, Adrian Hoban
  • Publication number: 20210314168
    Abstract: Technologies for providing certified telemetry data indicative of resource utilizations include a device with circuitry configured to obtain telemetry data indicative of a utilization of one or more device resources over a time period. The circuitry is additionally configured to validate the obtained telemetry data with a private key associated with the present device.
    Type: Application
    Filed: June 21, 2021
    Publication date: October 7, 2021
    Inventors: Francesc Guim Bernat, Johan Van De Groenendaal, Kshitij A. Doshi, Susanne M. Balle, Suraj Prabhakaran
  • Publication number: 20210303477
    Abstract: Examples described herein relate to a network interface device. In some examples, the network interface device includes a device interface; input/output circuitry to receive Ethernet compliant packets and output Ethernet compliant packets; circuitry to monitor a particular page for a rate of data copying among nodes within a group of two or more nodes; and circuitry to perform one or more actions based, at least in part, on the rate of data copying among the nodes within the group of two or more nodes to attempt to reduce a number of copy operations of the data among the nodes within the group of two or more nodes, wherein the group of two or more nodes are part of a distributed shared memory (DSM).
    Type: Application
    Filed: June 10, 2021
    Publication date: September 30, 2021
    Inventors: Kshitij A. DOSHI, Francesc GUIM BERNAT, Suraj PRABHAKARAN, Tushar Sudhakar GOHAD
  • Publication number: 20210297477
    Abstract: Technologies for matching security requirements for a function-as-a-service (FaaS) function request to an edge resource having security features matching the security requirements are disclosed. According to one embodiment of the present disclosure, an edge gateway device receives, from an edge device, a request to execute an accelerated function. The edge gateway device selects, as a function of one or more security requirements requested by the edge device, an edge resource to fulfill the request. The edge gateway device transmits the request to the edge resource to fulfill the request of the edge device, according to the one or more security requirements.
    Type: Application
    Filed: February 8, 2021
    Publication date: September 23, 2021
    Inventors: Kshitij Doshi, Francesc Guim Bernat, Suraj Prabhakaran, Ned M. Smith
  • Patent number: 11126568
    Abstract: Examples may include techniques to enable cache coherency of objects in a distributed shared memory (DSM) system, even where multiple nodes in the system manage the objects. Node memory space includes a tracking address space (TAS) where lines in the TAS correspond to objects in the (DSM). Access to the objects and the TAS is managed by a host fabric interface (HFI) caching agent in HFI of a node.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: September 21, 2021
    Assignee: INTEL CORPORATION
    Inventors: Francesc Guim Bernat, Kshitij A. Doshi, Robert G. Blankenship, Raj K. Ramanujan
  • Publication number: 20210288793
    Abstract: Technologies for providing streamlined provisioning of accelerated functions in a disaggregated architecture include a compute sled. The compute sled includes a network interface controller and circuitry to determine whether to accelerate a function of a workload executed by the compute sled, and send, to a memory sled and in response to a determination to accelerate the function, a data set on which the function is to operate. The circuitry is also to receive, from the memory sled, a service identifier indicative of a memory location independent handle for data associated with the function, send, to a compute device, a request to schedule acceleration of the function on the data set, receive a notification of completion of the acceleration of the function, and obtain, in response to receipt of the notification and using the service identifier, a resultant data set from the memory sled. The resultant data set was produced by an accelerator device during acceleration of the function on the data set.
    Type: Application
    Filed: May 27, 2021
    Publication date: September 16, 2021
    Inventors: Francesc GUIM BERNAT, Suraj PRABHAKARAN, Kshitij A. DOSHI, Timothy VERRALL
  • Publication number: 20210271733
    Abstract: Detailed are embodiments related to bit matrix multiplication in a processor. For example, in some embodiments a processor comprising: decode circuitry to decode an instruction have fields for an opcode, an identifier of a first source bit matrix, an identifier of a second source bit matrix, an identifier of a destination bit matrix, and an immediate; and execution circuitry to execute the decoded instruction to perform a multiplication of a matrix of S-bit elements of the identified first source bit matrix with S-bit elements of the identified second source bit matrix, wherein the multiplication and accumulation operations are selected by the operation selector and store a result of the matrix multiplication into the identified destination bit matrix, wherein S indicates a plural bit size is described.
    Type: Application
    Filed: January 22, 2021
    Publication date: September 2, 2021
    Inventors: Dmitry Y. Babokin, Kshitij A. Doshi, Vadim Sukhomlinov
  • Publication number: 20210273863
    Abstract: Embodiments may be generally directed to techniques to cause communication of a registration request between a first end-point and a second end-point of an end-to-end path, the registration request to establish resource load monitoring for one or more resources of the end-to-end path, receive one or more acknowledgements indicating resource loads for each of the one or more resources of the end-to-end path, at least one of the acknowledgements to indicate a resource of the one or more resources is not meeting a threshold requirement for the end-to-end path, and perform an action for communication traffic utilizing the one or more resources based on the acknowledgement.
    Type: Application
    Filed: March 16, 2021
    Publication date: September 2, 2021
    Applicant: INTEL CORPORATION
    Inventors: FRANCESC GUIM BERNAT, KSHITIJ A. DOSHI, DANIEL RIVAS BARRAGAN, MARK A. SCHMISSEUR, STEEN LARSEN
  • Publication number: 20210263779
    Abstract: Embodiments of systems, apparatuses and methods provide enhanced function as a service (FaaS) to users, e.g., computer developers and cloud service providers (CSPs). A computing system configured to provide such enhanced FaaS service include one or more controls architectural subsystems, software and orchestration subsystems, network and storage subsystems, and security subsystems. The computing system executes functions in response to events triggered by the users in an execution environment provided by the architectural subsystems, which represent an abstraction of execution management and shield the users from the burden of managing the execution. The software and orchestration subsystems allocate computing resources for the function execution by intelligently spinning up and down containers for function code with decreased instantiation latency and increased execution scalability while maintaining secured execution.
    Type: Application
    Filed: April 16, 2019
    Publication date: August 26, 2021
    Applicant: Intel Corporation
    Inventors: Mohammad R. Haghighat, Kshitij Doshi, Andrew J. Herdrich, Anup Mohan, Ravishankar R. Iyer, Mingqiu Sun, Krishna Bhuyan, Teck Joo Goh, Mohan J. Kumar, Michael Prinke, Michael Lemay, Leeor Peled, Jr-Shian Tsai, David M. Durham, Jeffrey D. Chamberlain, Vadim A. Sukhomlinov, Eric J. Dahlen, Sara Baghsorkhi, Harshad Sane, Areg Melik-Adamyan, Ravi Sahita, Dmitry Yurievich Babokin, Ian M. Steiner, Alexander Bachmutsky, Anil Rao, Mingwei Zhang, Nilesh K. Jain, Amin Firoozshahian, Baiju V. Patel, Wenyong Huang, Yeluri Raghuram
  • Publication number: 20210255897
    Abstract: Technologies for opportunistic acceleration overprovisioning for disaggregated architectures that include multiple processors on one or more compute devices. The disaggregated architecture to also include a compute device that includes at least one accelerator device and acceleration management circuitry. The acceleration management circuitry receives a plurality of job execution requests. The acceleration management circuitry to overprovision one or more accelerators by scheduling two or more job execution requests from among the plurality of job execution requests for execution by each accelerator device.
    Type: Application
    Filed: April 30, 2021
    Publication date: August 19, 2021
    Inventors: Francesc GUIM BERNAT, Suraj PRABHAKARAN, Daniel RIVAS BARRAGAN, Kshitij A. DOSHI
  • Patent number: 11093398
    Abstract: Embodiments may include systems and methods for performing remote memory operations in a shared memory address space. An apparatus includes a first network controller coupled to a first processor core. The first network controller processes a remote memory operation request, which is generated by a first memory coherency agent based on a first memory operation for an application operating on the first processor core. The remote memory operation request is associated with a remote memory address that is local to a second processor core coupled to the first processor core. The first network controller forwards the remote memory operation request to a second network controller coupled to the second processor core. The second processor core and the second network controller are to carry out a second memory operation to extend the first memory operation as a remote memory operation. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: August 17, 2021
    Assignee: Intel Corporation
    Inventors: Kshitij Doshi, Harald Servat, Francesc Guim Bernat
  • Publication number: 20210209469
    Abstract: Examples include techniques to manage training or trained models for deep learning applications. Examples include routing commands to configure a training model to be implemented by a training module or configure a trained model to be implemented by an inference module. The commands routed via out-of-band (OOB) link while training data for the training models or input data for the trained models are routed via inband links.
    Type: Application
    Filed: March 22, 2021
    Publication date: July 8, 2021
    Applicant: Intel Corporation
    Inventors: Francesc GUIM BERNAT, Suraj PRABHAKARAN, Kshitij A. DOSHI, Da-Ming CHIANG
  • Patent number: 11048528
    Abstract: Examples may include techniques for collective operations in a distributed architecture. A collective operation request message from a computing node causes collective operations at one or more target computing nodes communicatively coupled with the computing node through a network switch. The collective operation request message also causes the network switch to perform collective operations on collective operation results received from the one or more target computing nodes.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: June 29, 2021
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Kshitij A. Doshi, Daniel Rivas Barragan, Alejandro Duran Gonzalez
  • Publication number: 20210191789
    Abstract: A computing apparatus, including: a hardware computing platform; and logic to operate on the hardware computing platform, configured to: receive a microservice instance registration for a microservice accelerator, wherein the registration includes a microservice that the microservice accelerator is configured to provide, and a microservice connection capability indicating an ability of the microservice instance to communicate directly with other instances of the same or a different microservice; and log the registration in a microservice registration database.
    Type: Application
    Filed: December 4, 2020
    Publication date: June 24, 2021
    Applicant: Intel Corporation
    Inventors: Vadim Sukhomlinov, Kshitij A. Doshi
  • Patent number: 11044099
    Abstract: Technologies for providing certified telemetry data indicative of resource utilizations include a device with circuitry configured to obtain telemetry data indicative of a utilization of one or more device resources over a time period. The circuitry is additionally configured to sign the obtained telemetry data with a private key associated with the present device. Further, the circuitry is configured to send the signed telemetry data to a telemetry service for analysis.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: June 22, 2021
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Johan Van De Groenendaal, Kshitij A. Doshi, Susanne M. Balle, Suraj Prabhakaran
  • Patent number: 11044210
    Abstract: Technologies for performing switch-based collective operations in a fabric architecture include a network switch communicatively coupled to a plurality of computing nodes. The network switch is configured to identify sub-operations of a collective operation of a collective operation request received from one of the computing nodes and identify a plurality of operands for each of the sub-operations. The network switch is additionally configured to request a value for each of the operands from a corresponding target computing node at which the respective value is stored, determine a result of the collective operation as a function of the requested operand values, and transmit the result to the requesting computing node. Other embodiments are described herein.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: June 22, 2021
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Kshitij A. Doshi, Daniel Rivas Barragan, Alejandro Duran Gonzalez