Patents by Inventor Kshitij Bajaj
Kshitij Bajaj has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10645419Abstract: The present application relates to a system for verifying integrity of a stream of image frames including an encoder logic module and a decoder logic module. On source side, a test line insertion logic module receiving the stream is arranged upstream to the encoder logic module encoding the stream. The test line insertion logic module is configured to include one or more test lines into the image frames. A color coding is assigned to the one or more test lines. The color coding is selected from a coding scheme. On destination side, a test line detection and extraction logic module is arranged downstream to the decoder logic module receiving the encoded stream. The test line detection and extraction logic module extracts the color coding from the received image frames and verifies extracted coding data against the coding scheme. The coding data comprises at least the extracted color coding.Type: GrantFiled: January 3, 2017Date of Patent: May 5, 2020Assignee: NXP USA, Inc.Inventors: Dirk Wendel, Ritesh Agrawal, Kshitij Bajaj, Snehlata Gutgutia
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Patent number: 10283083Abstract: A layer selection module for a graphics display component, and method therefor. The layer selection module is arranged to identify a set M of active layers to be blended for a pixel, configure a display controller to generate composite pixel data for the pixel based on a subset N of up to n layers from the set M, determine whether a number m of active layers in the set M exceeds n, and output an indication of which active layers within the set M were excluded from the subset N, if it is determined that the number m of layers in the set M exceeds n.Type: GrantFiled: May 9, 2017Date of Patent: May 7, 2019Assignee: NXP USA, Inc.Inventors: Michael Andreas Staudenmaier, Kshitij Bajaj, Chanpreet Singh, Vincent Aubineau
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Patent number: 10217400Abstract: A display control apparatus comprising at least one memory element within which image data is stored, at least one display controller arranged to read from the, or each, memory element the image data and to output display data generated from the read image data to at least one display device. The display control apparatus further comprises at least one interface component via which the display controller is arranged to read image data from the memory element. The display control apparatus further comprises at least one interface bandwidth control component arranged to measure image data flow over the interface component from the memory element to the display controller, and configure a bandwidth for image data flow over the interface component from the memory element to the display controller based at least partly on the measured image data flow.Type: GrantFiled: January 6, 2016Date of Patent: February 26, 2019Assignee: NXP USA, Inc.Inventors: Michael Andreas Staudenmaier, Vincent Aubineau, Kshitij Bajaj
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Patent number: 10049428Abstract: A diagnostic data generation apparatus for a display controller comprises an underrun detector arranged to monitor, when in use, buffer depletion in order to detect an underrun condition. The underrun condition results from a data feed lag associated with a mismatch between a buffer fill rate and a predetermined output data rate. The underrun detector is arranged to generate diagnostic data in response to detection of the underrun condition, the diagnostic data identifying the underrun condition and a location in an array of pixels associated with the underrun condition.Type: GrantFiled: April 5, 2012Date of Patent: August 14, 2018Assignee: NXP USA, Inc.Inventors: Michael Staudenmaier, Kshitij Bajaj, Mehul Kumar, Steven McAslan, Sarthak Mittal
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Patent number: 10026151Abstract: A script-driven head-up display controller comprising an image warping unit and an image projection unit wherein the image warping unit is coupled to the image projection unit and is adapted to: receive a line-based warping descriptor comprising first information associated with a distortion caused by a non-flat display; and, in response to the reception of the line-based warping descriptor, the image warping unit is further adapted to, based on the line-based warping descriptor: fetch one or more lines of the source image; and, output to the image projection unit at least one output line of the output image associated with an electronic image warping of one or more pixels of the one or more input lines, and wherein the line-based warping descriptor further comprises second information associated with buffer management instructions calculated off-line.Type: GrantFiled: September 27, 2013Date of Patent: July 17, 2018Assignee: NXP USA, Inc.Inventors: Michael Andreas Staudenmaier, Kshitij Bajaj, Chanpreet Singh
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Patent number: 9900548Abstract: A display control unit is connected to a display and arranged to generate a video signal representing a sequence of video frames to be displayed consecutively on said display. The display control unit may include a first memory unit arranged to buffer a set of image descriptors; a second memory unit connected between said first memory unit and said display; an update unit connected to said first memory unit and arranged to update said image descriptors in said first memory unit and to generate a proceed signal only when said set of image descriptors in said first memory unit is up to date; a copy unit arranged to copy said image descriptors from said first memory unit to said second memory unit in response to said proceed signal; and a video unit arranged to generate said video signal on the basis of said image descriptors in said second memory unit.Type: GrantFiled: August 24, 2012Date of Patent: February 20, 2018Assignee: NXP USA, INC.Inventors: Michael Staudenmaier, Kshitij Bajaj, Mehul Kumar, Sarthak Mittal
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Publication number: 20180018936Abstract: A layer selection module for a graphics display component, and method therefor. The layer selection module is arranged to identify a set M of active layers to be blended for a pixel, configure a display controller to generate composite pixel data for the pixel based on a subset N of up to n layers from the set M, determine whether a number m of active layers in the set M exceeds n, and output an indication of which active layers within the set M were excluded from the subset N, if it is determined that the number m of layers in the set M exceeds n.Type: ApplicationFiled: May 9, 2017Publication date: January 18, 2018Inventors: Michael Andreas Staudenmaier, Kshitij Bajaj, Chanpreet Singh, Vincent Aubineau
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Publication number: 20170332104Abstract: The present application relates to a system for verifying integrity of a stream of image frames including an encoder logic module and a decoder logic module. On source side, a test line insertion logic module receiving the stream is arranged upstream to the encoder logic module encoding the stream. The test line insertion logic module is configured to include one or more test lines into the image frames. A color coding is assigned to the one or more test lines. The color coding is selected from a coding scheme. On destination side, a test line detection and extraction logic module is arranged downstream to the decoder logic module receiving the encoded stream. The test line detection and extraction logic module extracts the color coding from the received image frames and verifies extracted coding data against the coding scheme. The coding data comprises at least the extracted color coding.Type: ApplicationFiled: January 3, 2017Publication date: November 16, 2017Inventors: Dirk WENDEL, Ritesh AGRAWAL, Kshitij BAJAJ, Snehlata GUTGUTIA
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Patent number: 9811932Abstract: The present application relates to a display controller and display system and a method of operating thereof. At a filtering stage display image data are generated on the basis of received pixel-mapped image data. The filtering operation accepts a plurality of pixels out of the received image data as input values to generate a pixel of the display image data as output value. It is further determined whether the plurality of pixels being the input values to the filtering operation are marked. If all pixels thereof are marked, the output pixel being the output value is marked. The marked pixels in the display image data are validated on the basis reference data.Type: GrantFiled: April 17, 2015Date of Patent: November 7, 2017Assignee: NXP USA, INC.Inventors: Michael Andreas Staudenmaier, Kshitij Bajaj, Chanpreet Singh
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Patent number: 9710415Abstract: An asynchronous data transfer system includes a bus interface unit (BIU), a FIFO write logic module, a write pointer synchronizer, a write pointer validator, a FIFO read logic module, and an asynchronous FIFO buffer. The FIFO buffer receives a variable size data from the BIU and stores the variable size data at a write address. The FIFO write logic module generates a write pointer by encoding the write address using a Johnson code. The FIFO read logic module receives a synchronized write pointer at the asynchronous clock domain and generates a read address signal when the synchronized write pointer is a valid Johnson code format. The FIFO buffer transfers the variable size data to a processor based on the read address signal.Type: GrantFiled: November 3, 2014Date of Patent: July 18, 2017Assignee: NXP USA, INC.Inventors: Chanpreet Singh, Kshitij Bajaj, Abhineet Kumar Bhojak, Anisha Ladsaria, Tejbal Prasad
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Publication number: 20170039932Abstract: A display control apparatus comprising at least one memory element within which image data is stored, at least one display controller arranged to read from the, or each, memory element the image data and to output display data generated from the read image data to at least one display device. The display control apparatus further comprises at least one interface component via which the display controller is arranged to read image data from the memory element. The display control apparatus further comprises at least one interface bandwidth control component arranged to measure image data flow over the interface component from the memory element to the display controller, and configure a bandwidth for image data flow over the interface component from the memory element to the display controller based at least partly on the measured image data flow.Type: ApplicationFiled: January 6, 2016Publication date: February 9, 2017Inventors: Michael Andreas STAUDENMAIER, Vincent AUBINEAU, Kshitij BAJAJ
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Patent number: 9484004Abstract: A display controller includes first and second arbitrating units, a pixel data calculating unit, a latency measurement unit, and a clock divider. The first and second arbitrating units fetch first and second pixel data corresponding to at least one pixel from an external memory via a system bus. The pixel data calculating unit determines a size of the first and second pixel data. The latency measuring unit generates a first data rate value that is indicative of a latency of the system bus based on the size of the first and second pixel data. The clock divider receives a first clock signal modulation value corresponding to the first data rate value and alters a modulation of a reference clock signal. The graphics blending unit receives the first and second pixel data and provides blended pixel data to a display panel based on a modulated clock signal.Type: GrantFiled: February 17, 2015Date of Patent: November 1, 2016Assignee: FREESCALE SEMIOCNDUCTOR, INC.Inventors: Chanpreet Singh, Kshitij Bajaj, Nakul Grover, Michael A. Staudenmaier
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Publication number: 20160307346Abstract: The present application relates to a display controller and display system and a method of operating thereof. At a filtering stage display image data are generated on the basis of received pixel-mapped image data. The filtering operation accepts a plurality of pixels out of the received image data as input values to generate a pixel of the display image data as output value. It is further determined whether the plurality of pixels being the input values to the filtering operation are marked. If all pixels thereof are marked, the output pixel being the output value is marked. The marked pixels in the display image data are validated on the basis reference data.Type: ApplicationFiled: April 17, 2015Publication date: October 20, 2016Inventors: MICHAEL ANDREAS STAUDENMAIER, KSHITIJ BAJAJ, CHANPREET SINGH
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Publication number: 20160247255Abstract: A script-driven head-up display controller comprising an image warping unit and an image projection unit wherein the image warping unit is coupled to the image projection unit and is adapted to: receive a line-based warping descriptor comprising first information associated with a distortion caused by a non-flat display; and, in response to the reception of the line-based warping descriptor, the image warping unit is further adapted to, based on the line-based warping descriptor: fetch one or more lines of the source image; and, output to the image projection unit at least one output line of the output image associated with an electronic image warping of one or more pixels of the one or more input lines, and wherein the line-based warping descriptor further comprises second information associated with buffer management instructions calculated off-line.Type: ApplicationFiled: September 27, 2013Publication date: August 25, 2016Inventors: Michael Andreas STAUDENMAIER, Kshitij BAJAJ, Chanpreet SINGH
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Publication number: 20160240172Abstract: A display controller includes first and second arbitrating units, a pixel data calculating unit, a latency measurement unit, and a clock divider. The first and second arbitrating units fetch first and second pixel data corresponding to at least one pixel from an external memory via a system bus. The pixel data calculating unit determines a size of the first and second pixel data. The latency measuring unit generates a first data rate value that is indicative of a latency of the system bus based on the size of the first and second pixel data. The clock divider receives a first clock signal modulation value corresponding to the first data rate value and alters a modulation of a reference clock signal. The graphics blending unit receives the first and second pixel data and provides blended pixel data to a display panel based on a modulated clock signal.Type: ApplicationFiled: February 17, 2015Publication date: August 18, 2016Inventors: CHANPREET SINGH, Kshitij Bajaj, Nakul Grover, Michael A. Staudenmaier
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Publication number: 20160124889Abstract: An asynchronous data transfer system includes a bus interface unit (BIU), a FIFO write logic module, a write pointer synchronizer, a write pointer validator, a FIFO read logic module, and an asynchronous FIFO buffer. The FIFO buffer receives a variable size data from the BIU and stores the variable size data at a write address. The FIFO write logic module generates a write pointer by encoding the write address using a Johnson code. The FIFO read logic module receives a synchronized write pointer at the asynchronous clock domain and generates a read address signal when the synchronized write pointer is a valid Johnson code format. The FIFO buffer transfers the variable size data to a processor based on the read address signal.Type: ApplicationFiled: November 3, 2014Publication date: May 5, 2016Inventors: Chanpreet Singh, Kshitij Bajaj, Abhineet Kumar Bhojak, Anisha Ladsaria, Tejbal Prasad
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Publication number: 20150235633Abstract: A multi-layer display system for displaying images including a compressed image, in multiple planes, in a single frame, includes a compressed image decoder for decoding the compressed image, multiple arbiters for reading the decoded image data, and a decoder arbitration and semaphore control unit for splitting the compressed image into segments, assigning the segments to ones of the multiple planes, and allowing at least one arbiter to access the compressed image decoder to read the decoded data of the segment assigned to a plane mapped with the arbiter when the segment is being decoded.Type: ApplicationFiled: February 20, 2014Publication date: August 20, 2015Inventors: Chanpreet Singh, Kshitij Bajaj, Michael A. Staudenmaier
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Publication number: 20150208022Abstract: A display control unit is connected to a display and arranged to generate a video signal representing a sequence of video frames to be displayed consecutively on said display. The display control unit may include a first memory unit arranged to buffer a set of image descriptors; a second memory unit connected between said first memory unit and said display; an update unit connected to said first memory unit and arranged to update said image descriptors in said first memory unit and to generate a proceed signal only when said set of image descriptors in said first memory unit is up to date; a copy unit arranged to copy said image descriptors from said first memory unit to said second memory unit in response to said proceed signal; and a video unit arranged to generate said video signal on the basis of said image descriptors in said second memory unit.Type: ApplicationFiled: August 24, 2012Publication date: July 23, 2015Applicant: Freescale Semiconductor, Inc.Inventors: Michael Staudenmaier, Kshitij Bajaj, Mehul Kumar, Sarthak Mittal
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Publication number: 20150161759Abstract: A diagnostic data generation apparatus for a display controller comprises an underrun detector arranged to monitor, when in use, buffer depletion in order to detect an underrun condition. The underrun condition results from a data feed lag associated with a mismatch between a buffer fill rate and a predetermined output data rate.Type: ApplicationFiled: April 5, 2012Publication date: June 11, 2015Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Michael Staudenmaier, Kshitij Bajaj, Mehul Kumar, Steven Mcaslan, Sarthak Mittal
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Patent number: 8843791Abstract: A memory error management system connected to memory channels for managing errors detected in corresponding memory devices includes a reporting table including a list of historically reported errors, a binary value representing the current error status of the memory channels, a uniqueness check module for checking whether a historically reported error is reappearing as a current error, an error mask register for generating a masked binary value representing unique current errors in the memory channels, and a channel arbitration module for decoding the channel identifiers of corrupted memory channels from the masked binary value and storing the decoded channel identifiers into the reporting table.Type: GrantFiled: February 5, 2013Date of Patent: September 23, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Sarthak Mittal, Kshitij Bajaj, Prashant Bhargava