Patents by Inventor Kshitij Sudan
Kshitij Sudan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10635325Abstract: The apparatus operable to communicate with a memory comprises a persistent write tracker component operable to track frequency of persistent writes to at least one memory location during a time window; a threshold-exceeded detector component responsive to the tracker component and operable to detect excessive persistent writes to the at least one memory location during the time window; and a selective throttle component operable in response to a threshold-exceeded outcome from the detector component to cause selective throttling of persistent writes to the at least one memory location.Type: GrantFiled: November 22, 2016Date of Patent: April 28, 2020Assignee: ARM LimitedInventors: Kshitij Sudan, Stephan Diestelhorst, Michael Andrew Campbell
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Patent number: 10417141Abstract: A data processing system for managing at least first and second memories includes a caching manager and a translation lookaside buffer (TLB). The caching manager comprises hardware configured to transfer data between the memories and is configured to monitor accesses to the first memory by a processing device and transfer data in a frequently accessed region at a first address in the first memory to a region at a second address in the second memory. When the data has not been transferred to the second memory, the TLB stores a virtual address and a corresponding address in the first memory. However, when the data has been transferred to the second memory, the TLB stores the virtual address and a corresponding address in the second memory. A mapping between the addresses in the first and second memories may be stored in a shadow-address table.Type: GrantFiled: May 22, 2017Date of Patent: September 17, 2019Assignee: Arm LimitedInventors: Andrea Pellegrini, Kshitij Sudan, Ali Saidi, Wendy Arnott Elsasser
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Publication number: 20180336142Abstract: A data processing system for managing at least first and second memories includes a caching manager and a translation lookaside buffer (TLB). The caching manager comprises hardware configured to transfer data between the memories and is configured to monitor accesses to the first memory by a processing device and transfer data in a frequently accessed region at a first address in the first memory to a region at a second address in the second memory. When the data has not been transferred to the second memory, the TLB stores a virtual address and a corresponding address in the first memory. However, when the data has been transferred to the second memory, the TLB stores the virtual address and a corresponding address in the second memory. A mapping between the addresses in the first and second memories may be stored in a shadow-address table.Type: ApplicationFiled: May 22, 2017Publication date: November 22, 2018Applicant: ARM LtdInventors: Andrea PELLEGRINI, Kshitij SUDAN, Ali SAIDI, Wendy Arnott ELSASSER
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Patent number: 9996471Abstract: Cache line data and metadata are compressed and stored in first and, optionally, second memory regions, the metadata including an address tag When the compressed data fit entirely within a primary block in the first memory region, both data and metadata are retrieved in a single memory access. Otherwise, overflow data is stored in an overflow block in the second memory region. The first and second memory regions may be located in the same row of a DRAM, for example, or in different regions of a DRAM and may be configured to enable standard DRAM components to be used. Compression and decompression logic circuits may be included in a memory controller.Type: GrantFiled: June 28, 2016Date of Patent: June 12, 2018Assignee: Arm LimitedInventors: Ali Saidi, Kshitij Sudan, Andrew Joseph Rushing, Andreas Hansson, Michael Filippo
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Publication number: 20180143771Abstract: The apparatus operable to communicate with a memory comprises a persistent write tracker component operable to track frequency of persistent writes to at least one memory location during a time window; a threshold-exceeded detector component responsive to the tracker component and operable to detect excessive persistent writes to the at least one memory location during the time window; and a selective throttle component operable in response to a threshold-exceeded outcome from the detector component to cause selective throttling of persistent writes to the at least one memory location.Type: ApplicationFiled: November 22, 2016Publication date: May 24, 2018Applicant: ARM LimitedInventors: Kshitij SUDAN, Stephan DIESTELHORST, Michael Andrew CAMPBELL
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Publication number: 20170371793Abstract: Cache line data and metadata are compressed and stored in first and, optionally, second memory regions, the metadata including an address tag When the compressed data fit entirely within a primary block in the first memory region, both data and metadata are retrieved in a single memory access. Otherwise, overflow data is stored in an overflow block in the second memory region. The first and second memory regions may be located in the same row of a DRAM, for example, or in different regions of a DRAM and may be configured to enable standard DRAM components to be used. Compression and decompression logic circuits may be included in a memory controller.Type: ApplicationFiled: June 28, 2016Publication date: December 28, 2017Applicant: ARM LimitedInventors: Ali SAIDI, Kshitij SUDAN, Andrew Joseph RUSHING, Andreas HANSSON, Michael FILIPPO
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Patent number: 8738875Abstract: A system, and computer program product for increasing a capacity of a memory are provided in the illustrative embodiments. Using an application executing using a processor wherein the memory includes a set of ranks, the memory is configured to form a cold tier and a hot tier, the cold tier including a first subset of ranks from the set of ranks in the memory, and the hot tier including a second subset of ranks from the set of ranks in the memory. A determination is made whether a page to which a memory access request is directed is located in the cold tier in the memory. In response to the page being located in the cold tier of the memory, the processing of the memory access request is throttled by processing the memory access request with a delay.Type: GrantFiled: November 14, 2011Date of Patent: May 27, 2014Assignee: International Business Machines CorporationInventors: John Bruce Carter, Wei Huang, Karthick Rajamani, Kshitij Sudan, Joanne R. Rawson
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Patent number: 8719527Abstract: A method for increasing a capacity of a memory is provided in the illustrative embodiments. Using an application executing using a processor wherein the memory includes a set of ranks, the memory is configured to form a cold tier and a hot tier, the cold tier including a first subset of ranks from the set of ranks in the memory, and the hot tier including a second subset of ranks from the set of ranks in the memory. A determination is made whether a page to which a memory access request is directed is located in the cold tier in the memory. In response to the page being located in the cold tier of the memory, the processing of the memory access request is throttled by processing the memory access request with a delay.Type: GrantFiled: April 30, 2012Date of Patent: May 6, 2014Assignee: International Business Machines CorporationInventors: John Bruce Carter, Wei Huang, Karthick Rajamani, Kshitij Sudan, Joanne B. Rawson
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Publication number: 20130124814Abstract: A system, and computer program product for increasing a capacity of a memory are provided in the illustrative embodiments. Using an application executing using a processor wherein the memory includes a set of ranks, the memory is configured to form a cold tier and a hot tier, the cold tier including a first subset of ranks from the set of ranks in the memory, and the hot tier including a second subset of ranks from the set of ranks in the memory. A determination is made whether a page to which a memory access request is directed is located in the cold tier in the memory. In response to the page being located in the cold tier of the memory, the processing of the memory access request is throttled by processing the memory access request with a delay.Type: ApplicationFiled: November 14, 2011Publication date: May 16, 2013Applicant: International Business Machines CorporationInventors: John Bruce Carter, Wei Huang, Karthick Rajamani, Kshitij Sudan, Joanne R Rawson
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Publication number: 20130124810Abstract: A method for increasing a capacity of a memory is provided in the illustrative embodiments. Using an application executing using a processor wherein the memory includes a set of ranks, the memory is configured to form a cold tier and a hot tier, the cold tier including a first subset of ranks from the set of ranks in the memory, and the hot tier including a second subset of ranks from the set of ranks in the memory. A determination is made whether a page to which a memory access request is directed is located in the cold tier in the memory. In response to the page being located in the cold tier of the memory, the processing of the memory access request is throttled by processing the memory access request with a delay.Type: ApplicationFiled: April 30, 2012Publication date: May 16, 2013Applicant: International Business Machines CorporationInventors: John Bruce Carter, Wei Huang, Karthick Rajamani, Kshitij Sudan, Joanne B. Rawson