Patents by Inventor Kshitij YADAV

Kshitij YADAV has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12244138
    Abstract: A differential ESD circuit is provided for protecting a pair of differential terminals of an integrated circuit from electrostatic shock. A first diode couples between a first terminal in the pair of differential terminals and a first resistor that couples to a voltage node of the integrated circuit. Similarly, a second diode couples between a second terminal in the pair of differential terminals and a second resistor that couples to the voltage node of the integrated circuit. The first and second resistors isolate the first and second terminals from a capacitive loading that would otherwise exist from the first and second diodes.
    Type: Grant
    Filed: November 28, 2022
    Date of Patent: March 4, 2025
    Assignee: QUALCOMM Incorporated
    Inventors: Kshitij Yadav, Vijayakumar Dhanasekaran, Khaled Mahmoud Abdelfattah Aly, Ramkumar Sivakumar
  • Publication number: 20240178662
    Abstract: A differential ESD circuit is provided for protecting a pair of differential terminals of an integrated circuit from electrostatic shock. A first diode couples between a first terminal in the pair of differential terminals and a first resistor that couples to a voltage node of the integrated circuit. Similarly, a second diode couples between a second terminal in the pair of differential terminals and a second resistor that couples to the voltage node of the integrated circuit. The first and second resistors isolate the first and second terminals from a capacitive loading that would otherwise exist from the first and second diodes.
    Type: Application
    Filed: November 28, 2022
    Publication date: May 30, 2024
    Inventors: Kshitij YADAV, Vijayakumar DHANASEKARAN, Khaled Mahmoud ABDELFATTAH ALY, Ramkumar SIVAKUMAR
  • Publication number: 20240178663
    Abstract: An ESD trigger circuit is provided for protecting a pass transistor coupled to an integrated circuit terminal. The integrated circuit terminal couples through a diode to a voltage node. In response to an electrostatic shock at the integrated circuit terminal, the diode conducts charge to the voltage node to pulse a voltage of the voltage node. The ESD trigger circuit responds to the pulse of the voltage by coupling the voltage node to a gate of the pass transistor.
    Type: Application
    Filed: November 28, 2022
    Publication date: May 30, 2024
    Inventors: Kshitij YADAV, Vijayakumar DHANASEKARAN, Khaled Mahmoud ABDELFATTAH ALY, Ramkumar SIVAKUMAR, Dongyang TANG, Chienchung YANG
  • Publication number: 20240162718
    Abstract: Circuits and methods for suppression of negative transient voltage may be implemented in systems that combine high-speed data, audio, and charging at a plug. The circuits and methods for suppression of the negative transient voltage may include a first diode and transistor coupled in series between a pin and ground, where the transistor is controlled by an output of a voltage comparator that is also coupled to the first pin. A negative transient voltage event may cause the comparator to activate the transistor to sink a current through the diode.
    Type: Application
    Filed: November 14, 2022
    Publication date: May 16, 2024
    Inventors: Vijayakumar DHANASEKARAN, Ramkumar SIVAKUMAR, Kshitij YADAV, Khaled Mahmoud ABDELFATTAH ALY
  • Patent number: 11885836
    Abstract: Certain aspects of the present disclosure are generally directed to circuitry and techniques for voltage-to-current conversion. For example, certain aspects provide a circuit for signal amplification including a first amplifier; a first transistor, a gate of the first transistor being coupled to an output of the first amplifier and a drain of the first transistor being coupled to an output node of circuit; a first resistive element coupled between a first input node of the circuit and an input of the first amplifier; a second amplifier; a second transistor, a gate of the second transistor being coupled to an output of the second amplifier and a drain of the second transistor being coupled to the output node of circuit; and a second resistive element coupled between a second input node of the circuit and an input of the second amplifier.
    Type: Grant
    Filed: December 27, 2022
    Date of Patent: January 30, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Ramkumar Sivakumar, Jingxue Lu, Sherif Galal, Xinwang Zhang, Kshitij Yadav
  • Patent number: 11848696
    Abstract: An aspect includes an apparatus including a first amplifier; a first field effect transistor (FET) including a first source coupled to an output of the first amplifier, and a first drain for coupling to a first load; and a first gate drive circuit including an input coupled to the output of the first amplifier and an output coupled to a first gate of the first FET. Another aspect includes a method including amplifying a first audio signal using a first audio amplifier to generate a first voltage; generating a first gate voltage based on the first voltage; applying the first gate voltage to a first gate of a first field effect transistor (FET) coupled between the first audio amplifier and a first audio transducer; and applying the first voltage to a first source of the first FET.
    Type: Grant
    Filed: October 26, 2022
    Date of Patent: December 19, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Kshitij Yadav, Vijayakumar Dhanasekaran
  • Publication number: 20230137935
    Abstract: Certain aspects of the present disclosure are generally directed to circuitry and techniques for voltage-to-current conversion. For example, certain aspects provide a circuit for signal amplification including a first amplifier; a first transistor, a gate of the first transistor being coupled to an output of the first amplifier and a drain of the first transistor being coupled to an output node of circuit; a first resistive element coupled between a first input node of the circuit and an input of the first amplifier; a second amplifier; a second transistor, a gate of the second transistor being coupled to an output of the second amplifier and a drain of the second transistor being coupled to the output node of circuit; and a second resistive element coupled between a second input node of the circuit and an input of the second amplifier.
    Type: Application
    Filed: December 27, 2022
    Publication date: May 4, 2023
    Inventors: Ramkumar SIVAKUMAR, Jingxue LU, Sherif GALAL, Xinwang ZHANG, Kshitij YADAV
  • Publication number: 20230049081
    Abstract: An aspect includes an apparatus including a first amplifier; a first field effect transistor (FET) including a first source coupled to an output of the first amplifier, and a first drain for coupling to a first load; and a first gate drive circuit including an input coupled to the output of the first amplifier and an output coupled to a first gate of the first FET. Another aspect includes a method including amplifying a first audio signal using a first audio amplifier to generate a first voltage; generating a first gate voltage based on the first voltage; applying the first gate voltage to a first gate of a first field effect transistor (FET) coupled between the first audio amplifier and a first audio transducer; and applying the first voltage to a first source of the first FET.
    Type: Application
    Filed: October 26, 2022
    Publication date: February 16, 2023
    Inventors: Kshitij YADAV, Vijayakumar DHANASEKARAN
  • Patent number: 11536749
    Abstract: Certain aspects of the present disclosure are generally directed to circuitry and techniques for voltage-to-current conversion. For example, certain aspects provide a circuit for signal amplification including a first amplifier; a first transistor, a gate of the first transistor being coupled to an output of the first amplifier and a drain of the first transistor being coupled to an output node of circuit; a first resistive element coupled between a first input node of the circuit and an input of the first amplifier; a second amplifier; a second transistor, a gate of the second transistor being coupled to an output of the second amplifier and a drain of the second transistor being coupled to the output node of circuit; and a second resistive element coupled between a second input node of the circuit and an input of the second amplifier.
    Type: Grant
    Filed: January 21, 2021
    Date of Patent: December 27, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Ramkumar Sivakumar, Jingxue Lu, Sherif Galal, Xinwang Zhang, Kshitij Yadav
  • Patent number: 11522572
    Abstract: An aspect includes an apparatus including a first amplifier; a first field effect transistor (FET) including a first source coupled to an output of the first amplifier, and a first drain for coupling to a first load; and a first gate drive circuit including an input coupled to the output of the first amplifier and an output coupled to a first gate of the first FET. Another aspect includes a method including amplifying a first audio signal using a first audio amplifier to generate a first voltage; generating a first gate voltage based on the first voltage; applying the first gate voltage to a first gate of a first field effect transistor (FET) coupled between the first audio amplifier and a first audio transducer; and applying the first voltage to a first source of the first FET.
    Type: Grant
    Filed: May 18, 2021
    Date of Patent: December 6, 2022
    Assignee: QUALCOMM INCORPORATED
    Inventors: Kshitij Yadav, Vijayakumar Dhanasekaran
  • Publication number: 20220376730
    Abstract: An aspect includes an apparatus including a first amplifier; a first field effect transistor (FET) including a first source coupled to an output of the first amplifier, and a first drain for coupling to a first load; and a first gate drive circuit including an input coupled to the output of the first amplifier and an output coupled to a first gate of the first FET. Another aspect includes a method including amplifying a first audio signal using a first audio amplifier to generate a first voltage; generating a first gate voltage based on the first voltage; applying the first gate voltage to a first gate of a first field effect transistor (FET) coupled between the first audio amplifier and a first audio transducer; and applying the first voltage to a first source of the first FET.
    Type: Application
    Filed: May 18, 2021
    Publication date: November 24, 2022
    Inventors: Kshitij YADAV, Vijayakumar DHANASEKARAN
  • Patent number: 11348621
    Abstract: An apparatus for power supply mode switching includes a first voltage regulator to output a first voltage, a second voltage regulator to output a second voltage, a third voltage regulator to output a third voltage, an electronic load, a first switch between the first voltage regulator and the electronic load, a second switch between the second voltage regulator and the electronic load, and a third switch between the third voltage regulator and the electronic load. And, a method for power supply mode switching includes supplying power to an electronic load with a first voltage; switching to a second voltage; maintaining coupling of the electronic load with the second voltage while a voltage across the electronic load is less than a reference voltage; and switching to a third voltage when the voltage is greater than or equal to the reference voltage and the third voltage is less than the second voltage.
    Type: Grant
    Filed: August 21, 2020
    Date of Patent: May 31, 2022
    Assignee: QUALCOMM INCORPORATED
    Inventors: Kshitij Yadav, Vijayakumar Dhanasekaran, Yan Wang
  • Patent number: 11307604
    Abstract: In certain aspects, a clamp circuit includes a first current mirror having a first branch and a second branch, wherein the first current mirror is configured to mirror a current flowing through the first branch of the first current mirror to the second branch of the first current mirror. The clamp circuit also includes a second current mirror having a first branch and a second branch, wherein the second current mirror is configured to mirror a current flowing through the first branch of the second current mirror to the second branch of the second current mirror. The first branch of the first current mirror is coupled in series with the second branch of the second current mirror, and the second branch of the first current mirror is coupled in series with the first branch of the second current mirror.
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: April 19, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Kshitij Yadav, Sherif Galal
  • Publication number: 20220059138
    Abstract: An apparatus for power supply mode switching includes a first voltage regulator to output a first voltage, a second voltage regulator to output a second voltage, a third voltage regulator to output a third voltage, an electronic load, a first switch between the first voltage regulator and the electronic load, a second switch between the second voltage regulator and the electronic load, and a third switch between the third voltage regulator and the electronic load. And, a method for power supply mode switching includes supplying power to an electronic load with a first voltage; switching to a second voltage; maintaining coupling of the electronic load with the second voltage while a voltage across the electronic load is less than a reference voltage; and switching to a third voltage when the voltage is greater than or equal to the reference voltage and the third voltage is less than the second voltage.
    Type: Application
    Filed: August 21, 2020
    Publication date: February 24, 2022
    Inventors: Kshitij YADAV, Vijayakumar DHANASEKARAN, Yan WANG
  • Publication number: 20210231710
    Abstract: Certain aspects of the present disclosure are generally directed to circuitry and techniques for voltage-to-current conversion. For example, certain aspects provide a circuit for signal amplification including a first amplifier; a first transistor, a gate of the first transistor being coupled to an output of the first amplifier and a drain of the first transistor being coupled to an output node of circuit; a first resistive element coupled between a first input node of the circuit and an input of the first amplifier; a second amplifier; a second transistor, a gate of the second transistor being coupled to an output of the second amplifier and a drain of the second transistor being coupled to the output node of circuit; and a second resistive element coupled between a second input node of the circuit and an input of the second amplifier.
    Type: Application
    Filed: January 21, 2021
    Publication date: July 29, 2021
    Inventors: Ramkumar SIVAKUMAR, Jingxue LU, Sherif GALAL, Xinwang ZHANG, Kshitij YADAV
  • Publication number: 20210232169
    Abstract: In certain aspects, a clamp circuit includes a first current mirror having a first branch and a second branch, wherein the first current mirror is configured to mirror a current flowing through the first branch of the first current mirror to the second branch of the first current mirror. The clamp circuit also includes a second current mirror having a first branch and a second branch, wherein the second current mirror is configured to mirror a current flowing through the first branch of the second current mirror to the second branch of the second current mirror. The first branch of the first current mirror is coupled in series with the second branch of the second current mirror, and the second branch of the first current mirror is coupled in series with the first branch of the second current mirror.
    Type: Application
    Filed: January 7, 2021
    Publication date: July 29, 2021
    Inventors: Kshitij YADAV, Sherif GALAL
  • Patent number: 10855277
    Abstract: Certain aspects of the present disclosure provide circuitry connecting an output of voltage reference circuitry powered by a relatively high voltage to an input of a voltage buffer configured to generate a voltage lower than the high voltage. The connecting circuitry prevents the high voltage from reaching the input of the voltage buffer. One example electronic circuit generally includes a voltage reference circuit configured to be powered by a relatively higher voltage, a buffer circuit configured to generate a relatively lower voltage as compared to the relatively higher voltage, and circuitry coupled between an output of the voltage reference circuit and an input of the buffer circuit, the circuitry being configured to prevent the higher voltage from reaching the input of the buffer circuit.
    Type: Grant
    Filed: January 27, 2020
    Date of Patent: December 1, 2020
    Assignee: QUALCOMM Incorporated
    Inventor: Kshitij Yadav
  • Patent number: 10194234
    Abstract: An example apparatus includes an output jack including a ground pole and a power output pole, a power supply circuit configured to generate a power signal, a coupler circuit operably coupled to the ground pole and the power output pole of the output jack, such that the coupler circuit is configured to couple the power signal with a noise signal on the ground pole to generate a combined output signal on the power output pole.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: January 29, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Jingxue Lu, Vijayakumar Dhanasekaran, Meysam Azin, Arash Mashayekhi, Kshitij Yadav
  • Publication number: 20180352321
    Abstract: An example apparatus includes an output jack including a ground pole and a power output pole, a power supply circuit configured to generate a power signal, a coupler circuit operably coupled to the ground pole and the power output pole of the output jack, such that the coupler circuit is configured to couple the power signal with a noise signal on the ground pole to generate a combined output signal on the power output pole.
    Type: Application
    Filed: June 5, 2017
    Publication date: December 6, 2018
    Inventors: Jingxue LU, Vijayakumar DHANASEKARAN, Meysam AZIN, Arash MASHAYEKHI, Kshitij YADAV
  • Publication number: 20170063309
    Abstract: An audio amplifier, including: at least a two stage amplifier configured to receive an input signal and output an amplified output signal, the at least a two stage amplifier including at least one stage amplifier and an output stage amplifier; and an auxiliary stage amplifier having an input coupled to an output of the at least one stage amplifier and an input of the output stage amplifier.
    Type: Application
    Filed: June 17, 2016
    Publication date: March 2, 2017
    Inventors: Kshitij YADAV, Vijayakumar DHANASEKARAN