Abstract: A system for displaying image includes a driving circuit of a liquid crystal displaying device. The driving circuit of the liquid crystal displaying device includes a shift register, a voltage booster and a sample switch. The shift register receives an input pulse signal and shifts the input pulse signal to output an output pulse signal. The voltage booster is electrically connected with the shift register to receive the output pulse signal, and generates a boost voltage to output a boost signal within the enable time of the output pulse signal. The sample switch is electrically connected with the voltage booster to receive the boost signal. The boost signal controls the sample switch to sample a data signal.

Abstract: Display devices with low power consumption. In the display device, and first and second data lines, first and second gate lines, first and second supplemental lines, first and second pixels are provided. In the first pixel, a first transistor comprises a first terminal coupled to the first data line and a control terminal coupled to the first gate line, and a first storage capacitor comprises a first terminal coupled to the second terminal of the first transistor and a second terminal coupled to the first supplemental line. In the second pixel, a second transistor comprises a first terminal coupled to the second data line, and a control terminal coupled to the second gate line, and a second storage capacitor comprises a first terminal coupled to the second terminal of the second transistor and a second terminal coupled to the second supplemental line.

Abstract: Systems for displaying images. The system comprises a signal driving circuit with X+1 shift registers connected in series, generating X+1 output pulses in sequence according to a start pulse and a clock signal, and a logic unit coupled to the X+1 shift registers, generating Z driving signals in sequence according to the X+1 output pulses and Y enabling signals, wherein Y, X and Z are integers, Y>1, X>0 and Z>X.

Abstract: Display devices with low power consumption. In the display device, and first and second data lines, first and second gate lines, first and second supplemental lines, first and second pixels are provided. In the first pixel, a first transistor comprises a first terminal coupled to the first data line and a control terminal coupled to the first gate line, and a first storage capacitor comprises a first terminal coupled to the second terminal of the first transistor and a second terminal coupled to the first supplemental line. In the second pixel, a second transistor comprises a first terminal coupled to the second data line, and a control terminal coupled to the second gate line, and a second storage capacitor comprises a first terminal coupled to the second terminal of the second transistor and a second terminal coupled to the second supplemental line.

Abstract: A system for displaying image includes a driving circuit of a liquid crystal displaying device. The driving circuit of the liquid crystal displaying device includes a shift register, a voltage booster and a sample switch. The shift register receives an input pulse signal and shifts the input pulse signal to output an output pulse signal. The voltage booster is electrically connected with the shift register to receive the output pulse signal, and generates a boost voltage to output a boost signal within the enable time of the output pulse signal. The sample switch is electrically connected with the voltage booster to receive the boost signal. The boost signal controls the sample switch to sample a data signal.

Abstract: Architecture for transmitting a video signal and an control clock signal between an ASIC and a panel in a display is introduced. Two dummy shift registers (DSRs) and switches are used for sending out the control clock signal to an ASIC. The ASIC compares the control clock signal sent out from the DSR with the video signals desired to be sent to a display panel. Time difference between the control clock signal and the video signals is obtained by the ASIC and the video signals sent out from the ASIC are delayed with the time difference, in order to be synchronized with a shift pulse generated by operation of a shift register in the display.