Abstract: An embodiment of the present invention is a technique to enhance address translation performance. A register stores capability indicators to indicate capability supported by a circuit in a chipset for address translation of a guest physical address to a host physical address. A plurality of multi-level page tables is used for page walking in the address translation. Each of the page tables has page table entries. Each of the page table entries has at least an entry specifier corresponding to the capability indicated by the capability indicators.

Abstract: A printed circuit assembly, along with a server and method incorporating such printed circuit assembly, are disclosed for determining a storage configuration for use in a computer system via a simple hardware change. The printed circuit assembly may comprise a paddle board slot for connection to a paddle board for determining a storage configuration; a bus coupled to the paddle board; and a southbridge coupled to the bus, the southbridge comprising signal lines coupled to the paddle board slot through the bus. The storage configuration of the printed circuit assembly may be determined via the paddle board when the paddle board is connected to the paddle board slot.

Abstract: A fan control system for a computer system is provided. The fan control system includes a power sensor and a controller. The power sensor detects the power dissipated by a target device in the computer system. The controller calculates a suggested airflow speed required for the target device and thus outputs a control signal for controlling a fan within the computer system according to at least the dissipated power.

Abstract: A switch apparatus for a remote boot sequence of a network device is disclosed. The network device may comprise a processor and a network control circuit. The switch apparatus may comprise a first storage element for storing a first boot code, a second storage element for storing a second boot code, and a detect and switch circuit electrically connected to the network control circuit. The detect and switch circuit may selectively connect to one of the first storage element and the second storage element in response to whether there is a detected signal of a pluggable unit inserted into said network device, so that the processor executes the remote boot sequence in accordance with the boot code stored in the selected storage element.

Abstract: A fan control system for a computer system at the different altitudes is provided. The fan control system includes a current detector and a controller. The current sensing circuit detects a current of a fan at full speed. The controller outputs a control signal for controlling the fan within the computer system according to the fan current.

Abstract: A fan control system for a computer system is provided. The fan control system includes a power sensor and a controller. The power sensor detects the power dissipated by a target device in the computer system. The controller calculates a suggested airflow speed required for the target device and thus outputs a control signal for controlling a fan within the computer system according to at least the dissipated power.

Abstract: An embodiment of the present invention is a technique to enhance address translation performance. A register stores capability indicators to indicate capability supported by a circuit in a chipset for address translation of a guest physical address to a host physical address. A plurality of multi-level page tables is used for page walking in the address translation. Each of the page tables has page table entries. Each of the page table entries has at least an entry specifier corresponding to the capability indicated by the capability indicators.

Abstract: A printed circuit assembly, along with a server and method incorporating such printed circuit assembly, are disclosed for determining a storage configuration for use in a computer system via a simple hardware change. The printed circuit assembly may comprise a paddle board slot for connection to a paddle board for determining a storage configuration; a bus coupled to the paddle board; and a southbridge coupled to the bus, the southbridge comprising signal lines coupled to the paddle board slot through the bus. The storage configuration of the printed circuit assembly may be determined via the paddle board when the paddle board is connected to the paddle board slot.

Abstract: A switch apparatus for a remote boot sequence of a network device is disclosed. The network device may comprise a processor and a network control circuit. The switch apparatus may comprise a first storage element for storing a first boot code, a second storage element for storing a second boot code, and a detect and switch circuit electrically connected to the network control circuit. The detect and switch circuit may selectively connect to one of the first storage element and the second storage element in response to whether there is a detected signal of a pluggable unit inserted into said network device, so that the processor executes the remote boot sequence in accordance with the boot code stored in the selected storage element.

Abstract: An embodiment of the present invention is a technique to perform address translation. A table structure is indexed by a source identifier of an input/output (I/O) transaction specifying a guest physical address and requested by an I/O device to map the I/O device to a domain assigned to the I/O device. An address translation structure translates the guest physical address to a host physical address corresponding to the I/O transaction.

Abstract: An embodiment of the present invention is a technique to process faults in a direct memory access address translation. A register set stores global control or status information for fault processing of a fault generated by an input/output (I/O) transaction requested by an I/O device. An address translation structure translates a guest physical address to a host physical address. The guest physical address corresponds to the I/O transaction and is mapped to a domain. The address translation structure has at least an entry associated with the domain and domain-specific control information for the fault processing.

Abstract: An embodiment of the present invention is a technique to perform address translation. A table structure is indexed by a source identifier of an input/output (I/O) transaction specifying a guest physical address and requested by an I/O device to map the I/O device to a domain assigned to the I/O device. An address translation structure translates the guest physical address to a host physical address corresponding to the I/O transaction.

Abstract: An embodiment of the present invention is a technique to process faults in a direct memory access address translation. A register set stores global control or status information for fault processing of a fault generated by an input/output (I/O) transaction requested by an I/O device. An address translation structure translates a guest physical address to a host physical address. The guest physical address corresponds to the I/O transaction and is mapped to a domain. The address translation structure has at least an entry associated with the domain and domain-specific control information for the fault processing.

Abstract: An embodiment of the present invention is a technique to enhance address translation performance. A register stores capability indicators to indicate capability supported by a circuit in a chipset for address translation of a guest physical address to a host physical address. A plurality of multi-level page tables is used for page walking in the address translation. Each of the page tables has page table entries. Each of the page table entries has at least an entry specifier corresponding to the capability indicated by the capability indicators.