Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a redistribution layer including a first conductive feature and a second conductive feature, a first contact feature disposed over and electrically coupled to the first conductive feature, a second contact feature disposed over and electrically coupled to the second conductive feature, and a passivation feature extending from between the first conductive feature and the second conductive feature between the first contact feature and the second contact feature. The passivation feature includes a dielectric feature and a dielectric layer. The dielectric layer is disposed on a planar top surface of the dielectric feature and a composition of the dielectric feature is different from a composition of the dielectric layer.

Abstract: Semiconductor devices and methods of forming the same are provided. In some embodiments, a method includes receiving a workpiece having a redistribution layer disposed over and electrically coupled to an interconnect structure. In some embodiments, the method further includes patterning the redistribution layer to form a recess between and separating a first conductive feature and a second conductive feature of the redistribution layer, where corners of the first conductive feature and the second conductive feature are defined adjacent to and on either side of the recess. The method further includes depositing a first dielectric layer over the first conductive feature, the second conductive feature, and within the recess. The method further includes depositing a nitride layer over the first dielectric layer. In some examples, the method further includes removing portions of the nitride layer disposed over the corners of the first conductive feature and the second conductive feature.

Abstract: The present disclosure provides a circuit board including a first circuit layer, a dielectric layer on the first circuit layer, and a seed layer on the dielectric layer and directly contacting the first circuit layer, in which a top surface of the seed layer includes a levelled portion. The circuit board also includes a second circuit layer on the levelled portion of the seed layer, in which a grain boundary density of the second circuit layer is lower than that of a portion of the seed layer directly contacting the first circuit layer.

Abstract: An integrated circuit device includes a gate stack disposed over a substrate. A first L-shaped spacer is disposed along a first sidewall of the gate stack and a second L-shaped spacer is disposed along a second sidewall of the gate stack. The first L-shaped spacer and the second L-shaped spacer include silicon and carbon. A first source/drain epitaxy region and a second source/drain epitaxy region are disposed over the substrate. The gate stack is disposed between the first source/drain epitaxy region and the second source/drain epitaxy region. An interlevel dielectric (ILD) layer disposed over the substrate. The ILD layer is disposed between the first source/drain epitaxy region and a portion of the first L-shaped spacer disposed along the first sidewall of the gate stack and between the second source/drain epitaxy region and a portion of the second L-shaped spacer disposed along the second sidewall of the gate stack.

Abstract: A semiconductor package includes a first semiconductor device and a second semiconductor device. The first semiconductor device includes a first semiconductor substrate, a first bonding structure and a memory cell. The second semiconductor device is stacked over the first semiconductor device. The second semiconductor device includes a second semiconductor substrate, a second bonding structure in a second dielectric layer and a peripheral circuit between the second semiconductor substrate and the second bonding structure. The first bonding structure and the second bonding structure are bonded and disposed between the memory cell and the peripheral circuit, and the memory cell and the peripheral circuit are electrically connected through the first bonding structure and the second bonding structure.

Abstract: A gas detection and cleaning system for a vehicle is disclosed and includes an external modular base, a gas detection module and a cleaning device. The gas detection module is connected to a first external connection port of the external modular base to detect a gas in the vehicle and output the information datum. The information datum is transmitted through the first external connection port to a driving and controlling module of the external modular base, processed and converted into an actuation information datum for being externally outputted through a second external connection port of the external modular base. The cleaning device is connected with the second external connection port through an external port to receive the actuation information datum outputted from the second external connection port to actuate or close the cleaning device.

Abstract: A switch transistor protection device includes a voltage/current detection device and a determination device. The voltage/current detection device is electrically connected to a switch transistor, and used to detect a voltage of the gate, the body, the source or the drain of the switch transistor, or used to detect a current of the source or the drain of the switch transistor to generate a reference voltage. The determination device is electrically connected to the voltage/current detection device and the switch transistor, and used to determine whether the reference voltage exceeds an overcurrent voltage or a fixed maximum junction temperature voltage corresponding to a maximum junction temperature of the switch transistor. When the determination device determines the reference voltage exceeds the maximum junction temperature voltage or the overcurrent voltage, the determination device generates a control signal to the gate, the body, the source or the drain of the switch transistor.

Abstract: A power limiting circuit is provided to control operation power of a power device during operation. The power limiting circuit includes a detection circuit and a control circuit. The detection circuit is coupled to the power device. The detection circuit is configured to detect a cross voltage between an input terminal and an output terminal of the power device and generate at least one detection signal associated with the detected cross voltage. The control circuit is coupled to the detection circuit and the power device. The control circuit is configured to generate a control signal based on the at least one detection signal. The control signal is provided to enable or disable the power device to control the operation power of the power device.

Abstract: Bonding a full-bridge device and an LLC device in a stack, or forming the full-bridge device and the LLC device on a same substrate, rather than connecting the devices, reduces a chip area associated with a power converter including the full-bridge device and the LLC device. Additionally, the full-bridge device and the LLC device consume less power because parasitic inductance and capacitance are reduced. Additionally, raw materials and production time are conserved that would otherwise have been used to connect the full-bridge device and the LLC device (e.g., via wires).

Abstract: The present invention is concerned with a modified release pharmaceutical composition comprising an effective amount of at least one antipsychotic agent so that the antipsychotic agent(s) are released in such a manner to better accord with physiological and chronotherapeutic requirements of patients.

Abstract: An image sensor device includes a semiconductor device, a plurality of photo sensitive regions, a dielectric layer, a grid structure, and a plurality of convex dielectric lenses. The photo sensitive regions are in the semiconductor substrate. The dielectric layer is over a backside surface of the semiconductor substrate. The grid structure is over a backside surface of the dielectric layer. The grid structure includes a plurality of grid lines. Each of the grid lines comprises a lower portion and an upper portion forming an interface with the lower portion. The convex dielectric lenses are alternately arranged with the grid lines over the backside surface of the dielectric layer. Apexes of the plurality of convex dielectric lenses are higher than an interface between the upper portion and the lower portion of each of the grid lines.

Abstract: The invention discloses a method of improving a wire structure of a circuit board, comprising the following steps: providing a multi-layer circuit board, including an inner circuit and a surface circuit; forming an opening to expose the inner circuit; forming a first circuit layer in the opening; removing the first circuit layer, the first conductive circuit, and the surface circuit on the multi-layer circuit board and removing a part of the first circuit layer in the opening; forming an adhesion promoter layer in the opening and on the multi-layer circuit board; forming a second conductive circuit on the adhesion promoter layer and on the first conductive circuit layer in the opening; forming a photoresist layer on the second conductive circuit layer; forming a second circuit layer in the opening and on the multi-layer circuit board, and removing the photoresist layer and a part of the second conductive circuit.

Abstract: A band gap reference voltage generating circuit includes a reference voltage generating circuit, a current generating circuit, a current divider circuit, and a first connection path switching circuit. The reference voltage generating circuit forms a reference voltage on first and second current input terminals thereof. First and second input terminals of the current generating circuit are connected to the first and second current input terminals, respectively. The current generating circuit generates a first current to bias the reference voltage generating circuit. The current divider circuit includes a current input terminal, a first current output terminal, and a second current output terminal. The first connection path switching circuit switches connection paths between the first input terminal and the second input terminal of the current generating circuit, and the first current input terminal and the second current input terminal of the current divider circuit.

Abstract: An image sensor device includes a semiconductor device, a plurality of photo sensitive regions, a dielectric layer, a grid structure, and a plurality of convex dielectric lenses. The plurality of photo sensitive regions are in the semiconductor substrate. The dielectric layer is on a backside surface of the semiconductor substrate facing away from the plurality of photo sensitive regions. The grid structure is on a backside surface of the dielectric layer facing away from the semiconductor substrate. The grid structure includes a plurality of grid lines spaced from each other. The plurality of convex dielectric lenses are alternately arranged with the plurality of grid lines of the grid structure on the backside surface of the dielectric layer. Apexes of the plurality of convex dielectric lenses are lower than top ends of the plurality of grid lines of the grid structure.

Abstract: A band gap reference voltage generating circuit includes a reference voltage generating circuit, a current generating circuit, a current divider circuit, and a first connection path switching circuit. The reference voltage generating circuit forms a reference voltage on first and second current input terminals thereof. First and second input terminals of the current generating circuit are connected to the first and second current input terminals, respectively. The current generating circuit generates a first current to bias the reference voltage generating circuit. The current divider circuit includes a current input terminal, a first current output terminal, and a second current output terminal. The first connection path switching circuit switches connection paths between the first input terminal and the second input terminal of the current generating circuit, and the first current input terminal and the second current input terminal of the current divider circuit.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a gallium nitride (GaN) layer on a substrate; an aluminum gallium nitride (AlGaN) layer disposed on the GaN layer; a gate stack disposed on the AlGaN layer; a source feature and a drain feature disposed on the AlGaN layer and interposed by the gate stack; a dielectric material layer is disposed on the gate stack; and a field plate disposed on the dielectric material layer and electrically connected to the source feature, wherein the field plate includes a step-wise structure.

Abstract: A band gap reference voltage generating circuit includes a reference voltage generating circuit, a current generating circuit, a current divider circuit, and a first connection path switching circuit. The reference voltage generating circuit forms a reference voltage on first and second current input terminals thereof. First and second input terminals of the current generating circuit are connected to the first and second current input terminals, respectively. The current generating circuit generates a first current to bias the reference voltage generating circuit. The current divider circuit includes a current input terminal, a first current output terminal, and a second current output terminal. The first connection path switching circuit switches connection paths between the first input terminal and the second input terminal of the current generating circuit, and the first current input terminal and the second current input terminal of the current divider circuit.

Abstract: A band gap reference voltage generating circuit includes a reference voltage generating circuit, a current generating circuit, a current divider circuit, and a first connection path switching circuit. The reference voltage generating circuit forms a reference voltage on first and second current input terminals thereof. First and second input terminals of the current generating circuit are connected to the first and second current input terminals, respectively. The current generating circuit generates a first current to bias the reference voltage generating circuit. The current divider circuit includes a current input terminal, a first current output terminal, and a second current output terminal. The first connection path switching circuit switches connection paths between the first input terminal and the second input terminal of the current generating circuit, and the first current input terminal and the second current input terminal of the current divider circuit.

Abstract: An image sensor device includes a semiconductor device, a plurality of photo sensitive regions, a dielectric layer, a grid structure, and a plurality of convex dielectric lenses. The plurality of photo sensitive regions are in the semiconductor substrate. The dielectric layer is on a backside surface of the semiconductor substrate facing away from the plurality of photo sensitive regions. The grid structure is on a backside surface of the dielectric layer facing away from the semiconductor substrate. The grid structure includes a plurality of grid lines spaced from each other. The plurality of convex dielectric lenses are alternately arranged with the plurality of grid lines of the grid structure on the backside surface of the dielectric layer. Apexes of the plurality of convex dielectric lenses are lower than top ends of the plurality of grid lines of the grid structure.

Abstract: A method of manufacturing a semiconductor structure includes receiving a substrate including a first side and a second side opposite to the first side; forming a recess extending between the first side and the second side; and disposing a conductive material in the recess to form a conductive via, wherein the conductive via includes an interface, a first portion adjacent to the first side and a second portion adjacent to the second side, the interface is disposed between the first portion and the second portion, an average grain size of the first portion is substantially different from an average grain size of the second portion.